ethernet/sgi/ioc3-eth.c

81 	struct ioc3_ethregs *regs;
233 	       &ip->regs->emar_h);
238 	       &ip->regs->emar_l);
261 	struct ioc3_ethregs *regs = ip->regs;
263 	while (readl(&regs->micr) & MICR_BUSY)
266 	       &regs->micr);
267 	while (readl(&regs->micr) & MICR_BUSY)
270 	return readl(&regs->midr_r) & MIDR_DATA_MASK;
276 	struct ioc3_ethregs *regs = ip->regs;
278 	while (readl(&regs->micr) & MICR_BUSY)
280 	writel(data, &regs->midr_w);
281 	writel((phy << MICR_PHYADDR_SHIFT) | reg, &regs->micr);
282 	while (readl(&regs->micr) & MICR_BUSY)
291 	struct ioc3_ethregs *regs = ip->regs;
293 	dev->stats.collisions += readl(&regs->etcdc) & ETCDC_COLLCNT_MASK;
440 	writel((n_entry << 3) | ERPIR_ARM, &ip->regs->erpir);
448 	struct ioc3_ethregs *regs = ip->regs;
455 	etcir = readl(&regs->etcir);
471 		etcir = readl(&regs->etcir);		/* More pkts sent?  */
535 	struct ioc3_ethregs *regs = ip->regs;
538 	eisr = readl(&regs->eisr);
539 	writel(eisr, &regs->eisr);
540 	readl(&regs->eisr);				/* Flush */
555 	struct ioc3_ethregs *regs = ip->regs;
560 		writel(ETCSR_FD, &regs->etcsr);
563 		writel(ETCSR_HD, &regs->etcsr);
566 	writel(ip->emcr, &regs->emcr);
694 	struct ioc3_ethregs *regs = ip->regs;
700 	writel(readl(&regs->emcr) | (EMCR_BUFSIZ | EMCR_RAMPAR), &regs->emcr);
701 	readl(&regs->emcr); /* Flush */
710 		writel(readl(&regs->emcr) & ~EMCR_BUFSIZ, &regs->emcr);
719 	struct ioc3_ethregs *regs = ip->regs;
723 	writel(EMCR_RST, &regs->emcr);		/* Reset		*/
724 	readl(&regs->emcr);			/* Flush WB		*/
726 	writel(0, &regs->emcr);
727 	readl(&regs->emcr);
730 	writel(ERBAR_VAL, &regs->erbar);
731 	readl(&regs->etcdc);			/* Clear on read */
732 	writel(15, &regs->ercsr);		/* RX low watermark  */
733 	writel(0, &regs->ertr);			/* Interrupt immediately */
735 	writel(ip->ehar_h, &regs->ehar_h);
736 	writel(ip->ehar_l, &regs->ehar_l);
737 	writel(42, &regs->ersr);		/* XXX should be random */
742 	struct ioc3_ethregs *regs = ip->regs;
747 	writel(ring >> 32, &regs->erbr_h);
748 	writel(ring & 0xffffffff, &regs->erbr_l);
749 	writel(ip->rx_ci << 3, &regs->ercir);
750 	writel((ip->rx_pi << 3) | ERPIR_ARM, &regs->erpir);
757 	writel(ring >> 32, &regs->etbr_h);
758 	writel(ring & 0xffffffff, &regs->etbr_l);
759 	writel(ip->tx_pi << 7, &regs->etpir);
760 	writel(ip->tx_ci << 7, &regs->etcir);
761 	readl(&regs->etcir);				/* Flush */
765 	writel(ip->emcr, &regs->emcr);
768 	       EISR_TXEXPLICIT | EISR_TXMEMERR, &regs->eier);
769 	readl(&regs->eier);
774 	struct ioc3_ethregs *regs = ip->regs;
776 	writel(0, &regs->emcr);			/* Shutup */
777 	writel(0, &regs->eier);			/* Disable interrupts */
778 	readl(&regs->eier);			/* Flush */
833 	struct resource *regs;
837 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
838 	if (!regs) {
843 	if (ioc3eth_get_mac_addr(regs, mac_addr))
854 	ip->regs = devm_platform_ioremap_resource(pdev, 0);
855 	if (IS_ERR(ip->regs)) {
856 		err = PTR_ERR(ip->regs);
1088 	writel(produce << 7, &ip->regs->etpir);		/* Fire ... */
1237 	struct ioc3_ethregs *regs = ip->regs;
1245 		writel(ip->emcr, &regs->emcr);
1246 		readl(&regs->emcr);
1249 		writel(ip->emcr, &regs->emcr);		/* Clear promiscuous. */
1250 		readl(&regs->emcr);
1267 		writel(ip->ehar_h, &regs->ehar_h);
1268 		writel(ip->ehar_l, &regs->ehar_l);