ethernet/sfc/tc.c

860 	const struct flow_action_entry *fa;
863 	flow_action_for_each(i, fa, &fr->action) {
864 		switch (fa->id) {
980 	const struct flow_action_entry *fa;
987 	flow_action_for_each(i, fa, &fr->action) {
996 		switch (fa->id) {
998 			if (!fa->chain_index) {
1002 			rid = efx_tc_get_recirc_id(efx, fa->chain_index,
1009 			if (fa->hw_stats) {
1012 				if (!(fa->hw_stats & FLOW_ACTION_HW_STATS_DELAYED)) {
1015 							       fa->hw_stats);
1034 			if (fa->ct.action & (TCA_CT_ACT_COMMIT |
1039 			if (fa->ct.action & TCA_CT_ACT_CLEAR) {
1043 			if (fa->ct.action & (TCA_CT_ACT_NAT |
1049 			if (fa->ct.action) {
1051 						       fa->ct.action);
1054 			ct_zone = efx_tc_ct_register_zone(efx, fa->ct.zone,
1055 							  fa->ct.flow_table);
1064 					       fa->id);
1163 			    const struct flow_action_entry *fa,
1166 	switch (fa->mangle.htype) {
1168 		switch (fa->mangle.offset) {
1171 			if (fa->mangle.mask != ~EFX_TC_HDR_TYPE_TTL_MASK)
1177 			if ((fa->mangle.val & EFX_TC_HDR_TYPE_TTL_MASK) != U8_MAX)
1193 		switch (fa->mangle.offset) {
1196 			if (fa->mangle.mask != EFX_TC_HDR_TYPE_HLIMIT_MASK)
1202 			if ((fa->mangle.val >> 24) != U8_MAX)
1223 			       fa->mangle.htype, fa->mangle.offset,
1224 			       fa->mangle.val, fa->mangle.mask);
1232  * @fa:		FLOW_ACTION_MANGLE action metadata
1244 			 const struct flow_action_entry *fa,
1253 	switch (fa->mangle.htype) {
1262 		switch (fa->mangle.offset) {
1264 			if (fa->mangle.mask) {
1267 						       fa->mangle.mask);
1271 			mac32 = cpu_to_le32(fa->mangle.val);
1276 			if (fa->mangle.mask == 0xffff) {
1277 				mac16 = cpu_to_le16(fa->mangle.val >> 16);
1280 			} else if (fa->mangle.mask == 0xffff0000) {
1281 				mac16 = cpu_to_le16((u16)fa->mangle.val);
1287 						       fa->mangle.mask);
1292 			if (fa->mangle.mask) {
1295 						       fa->mangle.mask);
1298 			mac32 = cpu_to_le32(fa->mangle.val);
1304 					       fa->mangle.offset, fa->mangle.val, fa->mangle.mask);
1309 		switch (fa->mangle.offset) {
1317 			if (fa->mangle.mask != ~EFX_TC_HDR_TYPE_TTL_MASK) {
1320 						       fa->mangle.mask);
1353 			if ((fa->mangle.val & EFX_TC_HDR_TYPE_TTL_MASK) == tr_ttl) {
1362 					       fa->mangle.offset);
1367 		switch (fa->mangle.offset) {
1375 			if (fa->mangle.mask != EFX_TC_HDR_TYPE_HLIMIT_MASK) {
1378 						       fa->mangle.mask);
1412 			if ((fa->mangle.val >> 24) == tr_ttl) {
1425 				       fa->mangle.htype);
1681 	const struct flow_action_entry *fa;
1745 	flow_action_for_each(i, fa, &fr->action) {
1746 		switch (fa->id) {
1749 			to_efv = efx_tc_flower_lookup_efv(efx, fa->dev);
1832 	flow_action_for_each(i, fa, &fr->action) {
1835 		switch (fa->id) {
1842 			if (fa->hw_stats) {
1845 				if (!(fa->hw_stats & FLOW_ACTION_HW_STATS_DELAYED)) {
1848 							       fa->hw_stats);
1877 			to_efv = efx_tc_flower_lookup_efv(efx, fa->dev);
1905 			if (fa->id == FLOW_ACTION_REDIRECT)
1930 					       fa->id);
2081 	const struct flow_action_entry *fa;
2236 	flow_action_for_each(i, fa, &fr->action) {
2247 		if ((fa->id == FLOW_ACTION_REDIRECT ||
2248 		     fa->id == FLOW_ACTION_MIRRED ||
2249 		     fa->id == FLOW_ACTION_DROP) && fa->hw_stats) {
2271 			if (!(fa->hw_stats & FLOW_ACTION_HW_STATS_DELAYED)) {
2273 						       fa->hw_stats);
2289 		switch (fa->id) {
2313 						efx, encap_info, fa->dev, extack);
2343 				if (fa->id == FLOW_ACTION_REDIRECT)
2363 			to_efv = efx_tc_flower_lookup_efv(efx, fa->dev);
2383 			if (fa->id == FLOW_ACTION_REDIRECT)
2413 			tci = fa->vlan.vid & VLAN_VID_MASK;
2414 			tci |= fa->vlan.prio << VLAN_PRIO_SHIFT;
2416 			act->vlan_proto[act->vlan_push] = fa->vlan.proto;
2420 			rc = efx_tc_pedit_add(efx, act, fa, extack);
2425 			rc = efx_tc_mangle(efx, act, fa, &mung, extack, &match);
2440 			if (!fa->tunnel) {
2445 			encap_info = fa->tunnel;
2461 			if (fa->ct.action != TCA_CT_ACT_NAT) {
2463 				NL_SET_ERR_MSG_FMT_MOD(extack, "Can only offload CT 'nat' action in RHS rules, not %d", fa->ct.action);
2470 					       fa->id);