samsung/sxgbe/sxgbe_dma.c

21 static int sxgbe_dma_init(void __iomem *ioaddr, int fix_burst, int burst_map)
25 	reg_val = readl(ioaddr + SXGBE_DMA_SYSBUS_MODE_REG);
38 	writel(reg_val,	ioaddr + SXGBE_DMA_SYSBUS_MODE_REG);
43 static void sxgbe_dma_channel_init(void __iomem *ioaddr, int cha_num,
50 	reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num));
54 		writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num));
56 		reg_val = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num));
58 		writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num));
60 		reg_val = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num));
62 		writel(reg_val, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num));
67 	       ioaddr + SXGBE_DMA_CHA_TXDESC_HADD_REG(cha_num));
69 	       ioaddr + SXGBE_DMA_CHA_TXDESC_LADD_REG(cha_num));
72 	       ioaddr + SXGBE_DMA_CHA_RXDESC_HADD_REG(cha_num));
74 	       ioaddr + SXGBE_DMA_CHA_RXDESC_LADD_REG(cha_num));
82 	       ioaddr + SXGBE_DMA_CHA_TXDESC_TAILPTR_REG(cha_num));
86 	       ioaddr + SXGBE_DMA_CHA_RXDESC_LADD_REG(cha_num));
88 	writel(t_rsize - 1, ioaddr + SXGBE_DMA_CHA_TXDESC_RINGLEN_REG(cha_num));
89 	writel(r_rsize - 1, ioaddr + SXGBE_DMA_CHA_RXDESC_RINGLEN_REG(cha_num));
93 	       ioaddr + SXGBE_DMA_CHA_INT_ENABLE_REG(cha_num));
96 static void sxgbe_enable_dma_transmission(void __iomem *ioaddr, int cha_num)
100 	tx_config = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num));
102 	writel(tx_config, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num));
105 static void sxgbe_enable_dma_irq(void __iomem *ioaddr, int dma_cnum)
109 	       ioaddr + SXGBE_DMA_CHA_INT_ENABLE_REG(dma_cnum));
112 static void sxgbe_disable_dma_irq(void __iomem *ioaddr, int dma_cnum)
115 	writel(0, ioaddr + SXGBE_DMA_CHA_INT_ENABLE_REG(dma_cnum));
118 static void sxgbe_dma_start_tx(void __iomem *ioaddr, int tchannels)
124 		tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum));
127 		       ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum));
131 static void sxgbe_dma_start_tx_queue(void __iomem *ioaddr, int dma_cnum)
135 	tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum));
137 	writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum));
140 static void sxgbe_dma_stop_tx_queue(void __iomem *ioaddr, int dma_cnum)
144 	tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum));
146 	writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum));
149 static void sxgbe_dma_stop_tx(void __iomem *ioaddr, int tchannels)
155 		tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum));
157 		writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum));
161 static void sxgbe_dma_start_rx(void __iomem *ioaddr, int rchannels)
167 		rx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum));
170 		       ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum));
174 static void sxgbe_dma_stop_rx(void __iomem *ioaddr, int rchannels)
180 		rx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum));
182 		writel(rx_ctl_reg, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum));
186 static int sxgbe_tx_dma_int_status(void __iomem *ioaddr, int channel_no,
189 	u32 int_status = readl(ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no));
253 	writel(clear_val, ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no));
258 static int sxgbe_rx_dma_int_status(void __iomem *ioaddr, int channel_no,
261 	u32 int_status = readl(ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no));
319 	writel(clear_val, ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no));
325 static void sxgbe_dma_rx_watchdog(void __iomem *ioaddr, u32 riwt)
331 		       ioaddr + SXGBE_DMA_CHA_INT_RXWATCHTMR_REG(que_num));
335 static void sxgbe_enable_tso(void __iomem *ioaddr, u8 chan_num)
339 	ctrl = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(chan_num));
341 	writel(ctrl, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(chan_num));