Lines Matching defs:reg_val
168 u32 reg_val;
170 reg_val = readl(ioaddr + SXGBE_CORE_RX_CTL0_REG);
171 reg_val &= ~(SXGBE_CORE_RXQ_ENABLE_MASK << queue_num);
172 reg_val |= SXGBE_CORE_RXQ_ENABLE;
173 writel(reg_val, ioaddr + SXGBE_CORE_RX_CTL0_REG);
178 u32 reg_val;
180 reg_val = readl(ioaddr + SXGBE_CORE_RX_CTL0_REG);
181 reg_val &= ~(SXGBE_CORE_RXQ_ENABLE_MASK << queue_num);
182 reg_val |= SXGBE_CORE_RXQ_DISABLE;
183 writel(reg_val, ioaddr + SXGBE_CORE_RX_CTL0_REG);