Lines Matching refs:write_reg_high
283 write_reg_high(ioaddr, CMR1, CMR1h_RESET);
311 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE); /* Enable Tx and Rx. */
320 write_reg_high(ioaddr, CMR1, CMR1h_TxRxOFF); /* Disable Tx and Rx units. */
338 write_reg_high(ioaddr, CMR1, CMR1h_RESET | CMR1h_MUX);
409 write_reg_high(ioaddr, PROM_CMD, outval | EE_CLK_LOW);
410 write_reg_high(ioaddr, PROM_CMD, outval | EE_CLK_HIGH);
415 write_reg_high(ioaddr, PROM_CMD, EE_CLK_LOW & ~EE_CS);
464 write_reg_high(ioaddr, CMR1, CMR1h_RESET);
469 write_reg_high(ioaddr, CMR2, lp->addr_mode);
477 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE);
484 write_reg_high(ioaddr, IMR, ISRh_RxErr);
570 write_reg_high(ioaddr, IMR, 0);
585 write_reg_high(ioaddr, IMR, ISRh_RxErr);
634 write_reg_high(ioaddr, CMR2, CMR2h_OFF);
637 write_reg_high(ioaddr, ISR, ISRh_RxErr);
638 write_reg_high(ioaddr, CMR2, lp->addr_mode);
707 write_reg_high(ioaddr, IMR, ISRh_RxErr); /* Hmmm, really needed? */
777 write_reg_high(ioaddr, CMR1, CMR1h_TxENABLE);
778 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE);
839 write_reg_high(ioaddr, CMR2, CMR2h_OFF);
846 write_reg_high(ioaddr, CMR1, CMR1h_RESET | CMR1h_MUX);
863 write_reg_high(ioaddr, CMR2, lp->addr_mode);