Lines Matching refs:ahw
39 readl(((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
43 writel(value, ((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
46 #define QLCRDX(ahw, addr) \
47 readl(((ahw)->pci_base0) + ((ahw)->ext_reg_tbl[addr]))
50 #define QLCWRX(ahw, addr, value) \
51 writel(value, (((ahw)->pci_base0) + ((ahw)->ext_reg_tbl[addr])))