qlogic/qlcnic/qlcnic_83xx_init.c

136 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
146 	cur = adapter->ahw->idc.curr_state;
147 	prev = adapter->ahw->idc.prev_state;
151 		 adapter->ahw->idc.name[cur],
152 		 adapter->ahw->idc.name[prev]);
166 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
170 		seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
175 	QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
176 	adapter->ahw->idc.sec_counter = jiffies / HZ;
188 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
191 	QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
204 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
207 	QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
226 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
233 	QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
247 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
270 	QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
272 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
274 	QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
292 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
297 	QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
310 	seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
332 	ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
333 	presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
341 			val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
345 			QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
409 	for (i = 0; i < adapter->ahw->num_msix; i++) {
410 		adapter->ahw->intr_tbl[i].id = i;
411 		adapter->ahw->intr_tbl[i].enabled = 0;
412 		adapter->ahw->intr_tbl[i].src = 0;
450 	QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
468 	QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
484 	QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
501 	QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
518 	QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
540 	reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
541 	reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
616 	qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox);
648 	struct qlcnic_hardware_context *ahw = adapter->ahw;
652 	set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
654 	ahw->idc.quiesce_req = 0;
655 	ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
656 	ahw->idc.err_code = 0;
657 	ahw->idc.collect_dump = 0;
658 	ahw->reset_context = 0;
660 	ahw->idc.delay_reset = 0;
678 	struct qlcnic_hardware_context *ahw = adapter->ahw;
680 	if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
683 		if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
684 		    (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
708 	struct qlcnic_hardware_context *ahw = adapter->ahw;
711 	state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
713 		if (!ahw->idc.vnic_wait_limit--) {
722 		if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
727 			if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
731 			adapter->ahw->idc.vnic_state =  QLCNIC_DEV_NPAR_OPER;
741 	adapter->ahw->idc.err_code = -EIO;
796 	if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
798 		if (adapter->ahw->pci_func == owner)
820 	struct qlcnic_hardware_context *ahw = adapter->ahw;
821 	struct qlcnic_mailbox *mbx = ahw->mailbox;
826 	if (ahw->idc.state_entry(adapter))
830 		if (ahw->temp == QLCNIC_TEMP_PANIC) {
834 				adapter->ahw->temp);
843 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
859 	if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
868 	if (ahw->reset_context &&
870 		adapter->ahw->reset_context = 0;
876 	if (adapter->ahw->idc.quiesce_req) {
899 	struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
902 	if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
906 		if (adapter->ahw->nic_mode == QLCNIC_VNIC_MODE)
912 			adapter->ahw->idc.delay_reset = 1;
925 		if (adapter->ahw->idc.delay_reset) {
928 			adapter->ahw->idc.delay_reset = 0;
954 	struct qlcnic_hardware_context *ahw = adapter->ahw;
957 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
960 		if (ahw->pci_func == owner) {
969 	ahw->idc.err_code = -EIO;
985 	cur = adapter->ahw->idc.curr_state;
986 	prev = adapter->ahw->idc.prev_state;
1111 	state =	QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1115 		adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1117 		adapter->ahw->idc.curr_state = state;
1120 	switch (adapter->ahw->idc.curr_state) {
1143 	adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1147 	if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1149 				     adapter->ahw->idc.delay);
1167 	adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1168 	adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1169 	adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1170 	adapter->ahw->idc.err_code = 0;
1171 	adapter->ahw->idc.collect_dump = 0;
1172 	adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1175 	set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1180 		val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1182 		QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1195 	QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1201 	state =	QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1208 		QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1213 	adapter->ahw->idc.curr_state = state;
1220 		val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1222 		QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1260 	id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1267 		id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1272 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1274 	QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1275 	clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1294 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1304 		val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1306 		QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1308 		adapter->ahw->idc.collect_dump = 1;
1323 	dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1324 	size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1354 	struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info;
1378 	dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1654 		p_dev->ahw->reset.seq_error++;
1657 			__func__, p_dev->ahw->reset.seq_index);
1669 	u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1670 	int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1688 	struct qlcnic_hardware_context *ahw = p_dev->ahw;
1692 	if (ahw->reset.buff != NULL) {
1696 			kfree(ahw->reset.buff);
1701 	ahw->reset.seq_error = 0;
1702 	ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
1703 	if (ahw->reset.buff == NULL)
1706 	p_buff = p_dev->ahw->reset.buff;
1715 	ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1716 	addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1717 	p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1718 	count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1729 	ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1730 	ahw->reset.start_offset = ahw->reset.buff +
1731 				  ahw->reset.hdr->start_offset;
1732 	ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1758 		value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1929 				index = p_dev->ahw->reset.array_index;
1935 				p_dev->ahw->reset.array[index++] = j;
1938 					p_dev->ahw->reset.array_index = 1;
1946 	p_dev->ahw->reset.seq_end = 1;
1951 	p_dev->ahw->reset.template_end = 1;
1952 	if (p_dev->ahw->reset.seq_error == 0)
1981 	p_dev->ahw->reset.seq_end = 0;
1982 	p_dev->ahw->reset.template_end = 0;
1983 	entries = p_dev->ahw->reset.hdr->entries;
1984 	index = p_dev->ahw->reset.seq_index;
1986 	for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
2028 	p_dev->ahw->reset.seq_index = index;
2033 	p_dev->ahw->reset.seq_index = 0;
2035 	qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
2036 	if (p_dev->ahw->reset.seq_end != 1)
2042 	qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
2043 	if (p_dev->ahw->reset.template_end != 1)
2049 	qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
2050 	if (p_dev->ahw->reset.seq_end != 1)
2075 	struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info;
2081 	switch (adapter->ahw->post_mode) {
2113 		      adapter->ahw->post_mode);
2171 	struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info;
2198 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
2215 	if (adapter->ahw->run_post) {
2221 		adapter->ahw->run_post = false;
2253 	struct qlcnic_hardware_context *ahw = adapter->ahw;
2256 	err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
2260 	ahw->physical_port = (u8) nic_info.phys_port;
2261 	ahw->switch_mode = nic_info.switch_mode;
2262 	ahw->max_tx_ques = nic_info.max_tx_ques;
2263 	ahw->max_rx_ques = nic_info.max_rx_ques;
2264 	ahw->capabilities = nic_info.capabilities;
2265 	ahw->max_mac_filters = nic_info.max_mac_filters;
2266 	ahw->max_mtu = nic_info.max_mtu;
2279 	if (ahw->capabilities & QLC_83XX_ESWITCH_CAPABILITY)
2287 	struct qlcnic_hardware_context *ahw = adapter->ahw;
2296 		ahw->nic_mode = QLCNIC_VNIC_MODE;
2304 		ahw->nic_mode = QLCNIC_DEFAULT_MODE;
2306 		ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
2315 	adapter->max_sds_rings = min(ahw->max_rx_ques, max_sds_rings);
2316 	adapter->max_tx_rings = min(ahw->max_tx_ques, max_tx_rings);
2323 	struct qlcnic_hardware_context *ahw = adapter->ahw;
2325 	if (ahw->port_type == QLCNIC_XGBE) {
2331 	} else if (ahw->port_type == QLCNIC_GBE) {
2350 	adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2354 		 adapter->ahw->fw_hal_version);
2366 	presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2367 	audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2386 	struct qlcnic_hardware_context *ahw = adapter->ahw;
2391 	ahw->fw_info = kzalloc(sizeof(*fw_info), GFP_KERNEL);
2392 	if (!ahw->fw_info) {
2395 		fw_info = ahw->fw_info;
2425 	if (!adapter->ahw->msix_supported) {
2437 	struct qlcnic_hardware_context *ahw = adapter->ahw;
2441 	ahw->msix_supported = !!qlcnic_use_msi_x;
2446 		ahw->post_mode = QLC_83XX_POST_FAST_MODE;
2447 		ahw->run_post = true;
2450 		ahw->post_mode = QLC_83XX_POST_MEDIUM_MODE;
2451 		ahw->run_post = true;
2454 		ahw->post_mode = QLC_83XX_POST_SLOW_MODE;
2455 		ahw->run_post = true;
2458 		ahw->run_post = false;
2541 	qlcnic_83xx_free_mailbox(ahw->mailbox);
2542 	ahw->mailbox = NULL;
2549 	struct qlcnic_hardware_context *ahw = adapter->ahw;
2550 	struct qlc_83xx_idc *idc = &ahw->idc;
2555 	if (ahw->nic_mode == QLCNIC_VNIC_MODE)
2566 	struct qlcnic_hardware_context *ahw = adapter->ahw;
2567 	struct qlc_83xx_idc *idc = &ahw->idc;
2577 	if (ahw->pci_func == owner) {
2590 	struct qlcnic_hardware_context *ahw = adapter->ahw;
2591 	struct qlc_83xx_idc *idc = &ahw->idc;
2596 	if (ahw->pci_func == owner)