qlogic/netxen/netxen_nic_hw.c

16 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
18 #define MS_WIN(addr) (addr & 0x0ffc0000)
20 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
29 		void __iomem *addr, u32 data);
31 		void __iomem *addr);
351 #define MAC_HI(addr) \
352 	((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
353 #define MAC_LO(addr) \
354 	((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
407 static int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
417 	mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
418 	mac_hi = addr[2] | ((u32)addr[3] << 8) |
419 		((u32)addr[4] << 16) | ((u32)addr[5] << 24);
438 	u8 *addr = adapter->mac_addr;
447 	/* add broadcast addr to filter */
452 	/* add station addr to filter */
453 	val = MAC_HI(addr);
455 	val = MAC_LO(addr);
467 	u8 *addr = adapter->mac_addr;
476 	val = MAC_HI(addr);
478 	val = MAC_LO(addr);
490 		int index, u8 *addr)
495 	lo = MAC_LO(addr);
496 	hi = MAC_HI(addr);
542 		netxen_nic_set_mcast_addr(adapter, i++, ha->addr);
602 nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
616 	memcpy(mac_req->mac_addr, addr, ETH_ALEN);
622 		const u8 *addr, struct list_head *del_list)
631 		if (ether_addr_equal(addr, cur->mac_addr)) {
641 	memcpy(cur->mac_addr, addr, ETH_ALEN);
680 			nx_p3_nic_add_mac(adapter, ha->addr, &del_list);
729 static int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
731 	/* assuming caller has already copied new addr to netdev */
971 	int i, v, addr;
975 	addr = base;
978 		ret = netxen_rom_fast_read(adapter, addr, &v);
984 		addr += sizeof(u32);
988 		ret = netxen_rom_fast_read(adapter, addr, &v);
1080  *	 0 if no window access is needed. 'off' is set to 2M addr
1085 		ulong off, void __iomem **addr)
1101 		*addr = adapter->ahw.pci_base0 + m->start_2M +
1109 	*addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M +
1116  * Out: 'off' is 2M pci map addr
1123 	void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
1129 	writel(window, addr);
1130 	if (readl(addr) != window) {
1143 	void __iomem *addr;
1149 	addr = pci_base_offset(adapter, off);
1150 	if (addr)
1151 		return addr;
1159 		addr = *mem_ptr + (off & (PAGE_SIZE - 1));
1161 	return addr;
1168 	void __iomem *addr, *mem_ptr = NULL;
1170 	addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr);
1171 	if (!addr)
1175 		netxen_nic_io_write_128M(adapter, addr, data);
1179 		writel(data, addr);
1195 	void __iomem *addr, *mem_ptr = NULL;
1198 	addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr);
1199 	if (!addr)
1203 		data = netxen_nic_io_read_128M(adapter, addr);
1207 		data = readl(addr);
1224 	void __iomem *addr = NULL;
1226 	rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr);
1229 		writel(data, addr);
1238 		writel(data, addr);
1256 	void __iomem *addr = NULL;
1258 	rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr);
1261 		return readl(addr);
1268 		data = readl(addr);
1282 		void __iomem *addr, u32 data)
1285 	writel(data, addr);
1290 		void __iomem *addr)
1295 	val = readl(addr);
1302 		void __iomem *addr, u32 data)
1304 	writel(data, addr);
1308 		void __iomem *addr)
1310 	return readl(addr);
1316 	void __iomem *addr = NULL;
1321 			addr = PCI_OFFSET_SECOND_RANGE(adapter, offset);
1323 			addr = NETXEN_CRB_NORMALIZE(adapter, offset);
1326 					offset, &addr));
1329 	return addr;
1334 		u64 addr, u32 *start)
1336 	if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1337 		*start = (addr - NETXEN_ADDR_OCM0  + NETXEN_PCI_OCM0);
1339 	} else if (ADDR_IN_RANGE(addr,
1341 		*start = (addr - NETXEN_ADDR_OCM1 + NETXEN_PCI_OCM1);
1350 		u64 addr, u32 *start)
1354 	window = OCM_WIN(addr);
1361 	*start = NETXEN_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
1369 	void __iomem *addr, *mem_ptr = NULL;
1381 		addr = adapter->ahw.pci_base0 + start;
1383 		addr = pci_base_offset(adapter, start);
1384 		if (addr)
1395 		addr = mem_ptr + (start & (PAGE_SIZE-1));
1399 		*data = readq(addr);
1401 		writeq(*data, addr);
1414 	void __iomem *addr = adapter->ahw.pci_base0 +
1418 	*data = readq(addr);
1425 	void __iomem *addr = adapter->ahw.pci_base0 +
1429 	writeq(data, addr);
1447 	/* P2 has different SIU and MIU test agent base addr */
1525 	/* P2 has different SIU and MIU test agent base addr */
1938 	u32 opcode, read_value, addr;
1940 	addr = crtEntry->addr;
1950 					NX_WR_DUMP_REG(addr,
1955 					NX_RD_DUMP_REG(addr,
1958 					NX_WR_DUMP_REG(addr,
1963 					NX_RD_DUMP_REG(addr,
1967 					NX_WR_DUMP_REG(addr,
1972 					NX_RD_DUMP_REG(addr,
1976 					NX_WR_DUMP_REG(addr,
1982 					NX_RD_DUMP_REG(addr,
1994 					NX_RD_DUMP_REG(addr,
2009 						addr =
2012 					NX_RD_DUMP_REG(addr,
2030 						addr =
2034 					NX_WR_DUMP_REG(addr,
2060 		addr = addr + stride;
2071 	u64 addr, value = 0;
2074 	addr = (u64)memEntry->read_addr;
2079 		if (netxen_nic_pci_mem_read_2M(adapter, addr, &value))
2082 		addr += sizeof(value);
2094 	u32 op_count, addr, stride, value;
2096 	addr = crbEntry->addr;
2101 		NX_RD_DUMP_REG(addr, adapter->ahw.pci_base0, &value);
2102 		*data_buff++ = addr;
2104 		addr = addr + stride;
2150 	u32 addr, read_addr, read_value, cntrl_addr, tag_reg_addr;
2187 		addr = read_addr;
2189 			NX_RD_DUMP_REG(addr, adapter->ahw.pci_base0,
2192 			addr += cacheEntry->read_addr_stride;
2206 	u32 addr, read_addr, read_value, cntrl_addr, tag_reg_addr;
2222 		addr = read_addr;
2224 			NX_RD_DUMP_REG(addr,
2228 			addr += cacheEntry->read_addr_stride;
2243 	void __iomem *addr;
2244 	addr = (ocmEntry->read_addr + adapter->ahw.pci_base0);
2248 		value = readl(addr);
2250 		addr += ocmEntry->read_addr_stride;