Lines Matching refs:val64
120 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
1011 register u64 val64 = 0;
1014 val64 = readq(&bar0->pci_mode);
1015 mode = (u8)GET_PCI_MODE(val64);
1017 if (val64 & PCI_MODE_UNKNOWN_MODE)
1045 register u64 val64 = 0;
1050 val64 = readq(&bar0->pci_mode);
1051 mode = (u8)GET_PCI_MODE(val64);
1053 if (val64 & PCI_MODE_UNKNOWN_MODE)
1095 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1115 register u64 val64 = 0;
1127 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1129 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1131 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1137 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1138 writeq(val64, &bar0->tti_data1_mem);
1141 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1152 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1157 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1163 writeq(val64, &bar0->tti_data2_mem);
1165 val64 = TTI_CMD_MEM_WE |
1168 writeq(val64, &bar0->tti_command_mem);
1192 register u64 val64 = 0;
1212 val64 = 0xA500000000ULL;
1213 writeq(val64, &bar0->sw_reset);
1215 val64 = readq(&bar0->sw_reset);
1219 val64 = 0;
1220 writeq(val64, &bar0->sw_reset);
1222 val64 = readq(&bar0->sw_reset);
1229 val64 = readq(&bar0->adapter_status);
1230 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1240 val64 = readq(&bar0->mac_cfg);
1241 val64 |= MAC_RMAC_BCAST_ENABLE;
1243 writel((u32)val64, add);
1245 writel((u32) (val64 >> 32), (add + 4));
1248 val64 = readq(&bar0->mac_int_mask);
1249 val64 = readq(&bar0->mc_int_mask);
1250 val64 = readq(&bar0->xgxs_int_mask);
1253 val64 = dev->mtu;
1254 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1268 val64 = readq(&bar0->dtx_control);
1274 val64 = 0;
1275 writeq(val64, &bar0->tx_fifo_partition_0);
1276 writeq(val64, &bar0->tx_fifo_partition_1);
1277 writeq(val64, &bar0->tx_fifo_partition_2);
1278 writeq(val64, &bar0->tx_fifo_partition_3);
1283 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1293 writeq(val64, &bar0->tx_fifo_partition_0);
1294 val64 = 0;
1298 writeq(val64, &bar0->tx_fifo_partition_1);
1299 val64 = 0;
1303 writeq(val64, &bar0->tx_fifo_partition_2);
1304 val64 = 0;
1308 writeq(val64, &bar0->tx_fifo_partition_3);
1309 val64 = 0;
1325 val64 = readq(&bar0->tx_fifo_partition_0);
1327 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1333 val64 = readq(&bar0->tx_pa_cfg);
1334 val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1338 writeq(val64, &bar0->tx_pa_cfg);
1341 val64 = 0;
1345 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1347 writeq(val64, &bar0->rx_queue_priority);
1353 val64 = 0;
1364 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1368 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1372 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1376 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1380 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1384 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1388 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1392 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1396 writeq(val64, &bar0->rx_queue_cfg);
1404 val64 = 0x0;
1405 writeq(val64, &bar0->tx_w_round_robin_0);
1406 writeq(val64, &bar0->tx_w_round_robin_1);
1407 writeq(val64, &bar0->tx_w_round_robin_2);
1408 writeq(val64, &bar0->tx_w_round_robin_3);
1409 writeq(val64, &bar0->tx_w_round_robin_4);
1412 val64 = 0x0001000100010001ULL;
1413 writeq(val64, &bar0->tx_w_round_robin_0);
1414 writeq(val64, &bar0->tx_w_round_robin_1);
1415 writeq(val64, &bar0->tx_w_round_robin_2);
1416 writeq(val64, &bar0->tx_w_round_robin_3);
1417 val64 = 0x0001000100000000ULL;
1418 writeq(val64, &bar0->tx_w_round_robin_4);
1421 val64 = 0x0001020001020001ULL;
1422 writeq(val64, &bar0->tx_w_round_robin_0);
1423 val64 = 0x0200010200010200ULL;
1424 writeq(val64, &bar0->tx_w_round_robin_1);
1425 val64 = 0x0102000102000102ULL;
1426 writeq(val64, &bar0->tx_w_round_robin_2);
1427 val64 = 0x0001020001020001ULL;
1428 writeq(val64, &bar0->tx_w_round_robin_3);
1429 val64 = 0x0200010200000000ULL;
1430 writeq(val64, &bar0->tx_w_round_robin_4);
1433 val64 = 0x0001020300010203ULL;
1434 writeq(val64, &bar0->tx_w_round_robin_0);
1435 writeq(val64, &bar0->tx_w_round_robin_1);
1436 writeq(val64, &bar0->tx_w_round_robin_2);
1437 writeq(val64, &bar0->tx_w_round_robin_3);
1438 val64 = 0x0001020300000000ULL;
1439 writeq(val64, &bar0->tx_w_round_robin_4);
1442 val64 = 0x0001020304000102ULL;
1443 writeq(val64, &bar0->tx_w_round_robin_0);
1444 val64 = 0x0304000102030400ULL;
1445 writeq(val64, &bar0->tx_w_round_robin_1);
1446 val64 = 0x0102030400010203ULL;
1447 writeq(val64, &bar0->tx_w_round_robin_2);
1448 val64 = 0x0400010203040001ULL;
1449 writeq(val64, &bar0->tx_w_round_robin_3);
1450 val64 = 0x0203040000000000ULL;
1451 writeq(val64, &bar0->tx_w_round_robin_4);
1454 val64 = 0x0001020304050001ULL;
1455 writeq(val64, &bar0->tx_w_round_robin_0);
1456 val64 = 0x0203040500010203ULL;
1457 writeq(val64, &bar0->tx_w_round_robin_1);
1458 val64 = 0x0405000102030405ULL;
1459 writeq(val64, &bar0->tx_w_round_robin_2);
1460 val64 = 0x0001020304050001ULL;
1461 writeq(val64, &bar0->tx_w_round_robin_3);
1462 val64 = 0x0203040500000000ULL;
1463 writeq(val64, &bar0->tx_w_round_robin_4);
1466 val64 = 0x0001020304050600ULL;
1467 writeq(val64, &bar0->tx_w_round_robin_0);
1468 val64 = 0x0102030405060001ULL;
1469 writeq(val64, &bar0->tx_w_round_robin_1);
1470 val64 = 0x0203040506000102ULL;
1471 writeq(val64, &bar0->tx_w_round_robin_2);
1472 val64 = 0x0304050600010203ULL;
1473 writeq(val64, &bar0->tx_w_round_robin_3);
1474 val64 = 0x0405060000000000ULL;
1475 writeq(val64, &bar0->tx_w_round_robin_4);
1478 val64 = 0x0001020304050607ULL;
1479 writeq(val64, &bar0->tx_w_round_robin_0);
1480 writeq(val64, &bar0->tx_w_round_robin_1);
1481 writeq(val64, &bar0->tx_w_round_robin_2);
1482 writeq(val64, &bar0->tx_w_round_robin_3);
1483 val64 = 0x0001020300000000ULL;
1484 writeq(val64, &bar0->tx_w_round_robin_4);
1489 val64 = readq(&bar0->tx_fifo_partition_0);
1490 val64 |= (TX_FIFO_PARTITION_EN);
1491 writeq(val64, &bar0->tx_fifo_partition_0);
1499 val64 = 0x0;
1500 writeq(val64, &bar0->rx_w_round_robin_0);
1501 writeq(val64, &bar0->rx_w_round_robin_1);
1502 writeq(val64, &bar0->rx_w_round_robin_2);
1503 writeq(val64, &bar0->rx_w_round_robin_3);
1504 writeq(val64, &bar0->rx_w_round_robin_4);
1506 val64 = 0x8080808080808080ULL;
1507 writeq(val64, &bar0->rts_qos_steering);
1510 val64 = 0x0001000100010001ULL;
1511 writeq(val64, &bar0->rx_w_round_robin_0);
1512 writeq(val64, &bar0->rx_w_round_robin_1);
1513 writeq(val64, &bar0->rx_w_round_robin_2);
1514 writeq(val64, &bar0->rx_w_round_robin_3);
1515 val64 = 0x0001000100000000ULL;
1516 writeq(val64, &bar0->rx_w_round_robin_4);
1518 val64 = 0x8080808040404040ULL;
1519 writeq(val64, &bar0->rts_qos_steering);
1522 val64 = 0x0001020001020001ULL;
1523 writeq(val64, &bar0->rx_w_round_robin_0);
1524 val64 = 0x0200010200010200ULL;
1525 writeq(val64, &bar0->rx_w_round_robin_1);
1526 val64 = 0x0102000102000102ULL;
1527 writeq(val64, &bar0->rx_w_round_robin_2);
1528 val64 = 0x0001020001020001ULL;
1529 writeq(val64, &bar0->rx_w_round_robin_3);
1530 val64 = 0x0200010200000000ULL;
1531 writeq(val64, &bar0->rx_w_round_robin_4);
1533 val64 = 0x8080804040402020ULL;
1534 writeq(val64, &bar0->rts_qos_steering);
1537 val64 = 0x0001020300010203ULL;
1538 writeq(val64, &bar0->rx_w_round_robin_0);
1539 writeq(val64, &bar0->rx_w_round_robin_1);
1540 writeq(val64, &bar0->rx_w_round_robin_2);
1541 writeq(val64, &bar0->rx_w_round_robin_3);
1542 val64 = 0x0001020300000000ULL;
1543 writeq(val64, &bar0->rx_w_round_robin_4);
1545 val64 = 0x8080404020201010ULL;
1546 writeq(val64, &bar0->rts_qos_steering);
1549 val64 = 0x0001020304000102ULL;
1550 writeq(val64, &bar0->rx_w_round_robin_0);
1551 val64 = 0x0304000102030400ULL;
1552 writeq(val64, &bar0->rx_w_round_robin_1);
1553 val64 = 0x0102030400010203ULL;
1554 writeq(val64, &bar0->rx_w_round_robin_2);
1555 val64 = 0x0400010203040001ULL;
1556 writeq(val64, &bar0->rx_w_round_robin_3);
1557 val64 = 0x0203040000000000ULL;
1558 writeq(val64, &bar0->rx_w_round_robin_4);
1560 val64 = 0x8080404020201008ULL;
1561 writeq(val64, &bar0->rts_qos_steering);
1564 val64 = 0x0001020304050001ULL;
1565 writeq(val64, &bar0->rx_w_round_robin_0);
1566 val64 = 0x0203040500010203ULL;
1567 writeq(val64, &bar0->rx_w_round_robin_1);
1568 val64 = 0x0405000102030405ULL;
1569 writeq(val64, &bar0->rx_w_round_robin_2);
1570 val64 = 0x0001020304050001ULL;
1571 writeq(val64, &bar0->rx_w_round_robin_3);
1572 val64 = 0x0203040500000000ULL;
1573 writeq(val64, &bar0->rx_w_round_robin_4);
1575 val64 = 0x8080404020100804ULL;
1576 writeq(val64, &bar0->rts_qos_steering);
1579 val64 = 0x0001020304050600ULL;
1580 writeq(val64, &bar0->rx_w_round_robin_0);
1581 val64 = 0x0102030405060001ULL;
1582 writeq(val64, &bar0->rx_w_round_robin_1);
1583 val64 = 0x0203040506000102ULL;
1584 writeq(val64, &bar0->rx_w_round_robin_2);
1585 val64 = 0x0304050600010203ULL;
1586 writeq(val64, &bar0->rx_w_round_robin_3);
1587 val64 = 0x0405060000000000ULL;
1588 writeq(val64, &bar0->rx_w_round_robin_4);
1590 val64 = 0x8080402010080402ULL;
1591 writeq(val64, &bar0->rts_qos_steering);
1594 val64 = 0x0001020304050607ULL;
1595 writeq(val64, &bar0->rx_w_round_robin_0);
1596 writeq(val64, &bar0->rx_w_round_robin_1);
1597 writeq(val64, &bar0->rx_w_round_robin_2);
1598 writeq(val64, &bar0->rx_w_round_robin_3);
1599 val64 = 0x0001020300000000ULL;
1600 writeq(val64, &bar0->rx_w_round_robin_4);
1602 val64 = 0x8040201008040201ULL;
1603 writeq(val64, &bar0->rts_qos_steering);
1608 val64 = 0;
1610 writeq(val64, &bar0->rts_frm_len_n[i]);
1613 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1615 writeq(val64, &bar0->rts_frm_len_n[i]);
1647 val64 = STAT_BC(0x320);
1648 writeq(val64, &bar0->stat_byte_cnt);
1655 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1657 writeq(val64, &bar0->mac_link_util);
1675 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1677 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1678 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1683 writeq(val64, &bar0->rti_data1_mem);
1685 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1688 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1691 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1693 writeq(val64, &bar0->rti_data2_mem);
1696 val64 = RTI_CMD_MEM_WE |
1699 writeq(val64, &bar0->rti_command_mem);
1710 val64 = readq(&bar0->rti_command_mem);
1711 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1733 val64 = readq(&bar0->mac_cfg);
1734 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1736 writel((u32) (val64), add);
1738 writel((u32) (val64 >> 32), (add + 4));
1739 val64 = readq(&bar0->mac_cfg);
1743 val64 = readq(&bar0->mac_cfg);
1744 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1746 writeq(val64, &bar0->mac_cfg);
1749 writel((u32) (val64), add);
1751 writel((u32) (val64 >> 32), (add + 4));
1758 val64 = readq(&bar0->rmac_pause_cfg);
1759 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1760 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1761 writeq(val64, &bar0->rmac_pause_cfg);
1769 val64 = 0;
1771 val64 |= (((u64)0xFF00 |
1775 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1777 val64 = 0;
1779 val64 |= (((u64)0xFF00 |
1783 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1789 val64 = readq(&bar0->pic_control);
1790 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1791 writeq(val64, &bar0->pic_control);
1804 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1806 writeq(val64, &bar0->misc_control);
1807 val64 = readq(&bar0->pic_control2);
1808 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1809 writeq(val64, &bar0->pic_control2);
1812 val64 = TMAC_AVG_IPG(0x17);
1813 writeq(val64, &bar0->tmac_avg_ipg);
2080 u64 val64 = readq(&bar0->adapter_status);
2086 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2089 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2094 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2098 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2122 u64 val64 = readq(&bar0->adapter_status);
2125 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2129 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2133 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2137 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2141 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2145 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2149 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2153 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2163 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2169 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2214 register u64 val64 = 0;
2226 val64 = readq(&bar0->prc_ctrl_n[i]);
2228 val64 |= PRC_CTRL_RC_ENABLED;
2230 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2232 val64 |= PRC_CTRL_GROUP_READS;
2233 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2234 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2235 writeq(val64, &bar0->prc_ctrl_n[i]);
2240 val64 = readq(&bar0->rx_pa_cfg);
2241 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2242 writeq(val64, &bar0->rx_pa_cfg);
2246 val64 = readq(&bar0->rx_pa_cfg);
2247 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2248 writeq(val64, &bar0->rx_pa_cfg);
2257 val64 = readq(&bar0->mc_rldram_mrs);
2258 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2259 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2260 val64 = readq(&bar0->mc_rldram_mrs);
2265 val64 = readq(&bar0->adapter_control);
2266 val64 &= ~ADAPTER_ECC_EN;
2267 writeq(val64, &bar0->adapter_control);
2273 val64 = readq(&bar0->adapter_status);
2277 dev->name, (unsigned long long)val64);
2290 val64 = readq(&bar0->adapter_control);
2291 val64 |= ADAPTER_EOI_TX_ON;
2292 writeq(val64, &bar0->adapter_control);
2305 val64 = readq(&bar0->gpio_control);
2306 val64 |= 0x0000800000000000ULL;
2307 writeq(val64, &bar0->gpio_control);
2308 val64 = 0x0411040400000000ULL;
2309 writeq(val64, (void __iomem *)bar0 + 0x2700);
2416 register u64 val64 = 0;
2426 val64 = readq(&bar0->adapter_control);
2427 val64 &= ~(ADAPTER_CNTL_EN);
2428 writeq(val64, &bar0->adapter_control);
2836 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2846 writeq(val64, &bar0->rx_traffic_int);
2847 writeq(val64, &bar0->tx_traffic_int);
3089 u64 val64;
3094 val64 = MDIO_MMD_INDX_ADDR(addr) |
3097 writeq(val64, &bar0->mdio_control);
3098 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3099 writeq(val64, &bar0->mdio_control);
3103 val64 = MDIO_MMD_INDX_ADDR(addr) |
3108 writeq(val64, &bar0->mdio_control);
3109 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3110 writeq(val64, &bar0->mdio_control);
3113 val64 = MDIO_MMD_INDX_ADDR(addr) |
3117 writeq(val64, &bar0->mdio_control);
3118 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3119 writeq(val64, &bar0->mdio_control);
3134 u64 val64 = 0x0;
3140 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3143 writeq(val64, &bar0->mdio_control);
3144 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3145 writeq(val64, &bar0->mdio_control);
3149 val64 = MDIO_MMD_INDX_ADDR(addr) |
3153 writeq(val64, &bar0->mdio_control);
3154 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3155 writeq(val64, &bar0->mdio_control);
3181 u64 val64;
3188 val64 = *regs_stat & mask;
3189 val64 = val64 >> (index * 0x2);
3190 val64 = val64 + 1;
3191 if (val64 == 3) {
3215 val64 = 0x0;
3217 val64 = val64 << (index * 0x2);
3218 *regs_stat = (*regs_stat & (~mask)) | (val64);
3237 u64 val64 = 0x0;
3246 val64 = 0x0;
3247 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3248 if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
3251 (unsigned long long)val64);
3256 if (val64 != MDIO_CTRL1_SPEED10G) {
3259 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3266 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3270 val64 = 0x0;
3271 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3273 flag = CHECKBIT(val64, 0x7);
3279 if (CHECKBIT(val64, 0x6))
3282 flag = CHECKBIT(val64, 0x3);
3288 if (CHECKBIT(val64, 0x2))
3291 flag = CHECKBIT(val64, 0x1);
3297 if (CHECKBIT(val64, 0x0))
3302 val64 = 0x0;
3303 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3305 if (CHECKBIT(val64, 0x7))
3308 if (CHECKBIT(val64, 0x6))
3311 if (CHECKBIT(val64, 0x3))
3314 if (CHECKBIT(val64, 0x2))
3317 if (CHECKBIT(val64, 0x1))
3320 if (CHECKBIT(val64, 0x0))
3342 u64 val64;
3348 val64 = readq(addr);
3350 if (!(val64 & busy_bit)) {
3355 if (val64 & busy_bit) {
3404 u64 val64;
3419 val64 = SW_RESET_ALL;
3420 writeq(val64, &bar0->sw_reset);
3495 val64 = readq(&bar0->gpio_control);
3496 val64 |= 0x0000800000000000ULL;
3497 writeq(val64, &bar0->gpio_control);
3498 val64 = 0x0411040400000000ULL;
3499 writeq(val64, (void __iomem *)bar0 + 0x2700);
3507 val64 = readq(&bar0->pcc_err_reg);
3508 writeq(val64, &bar0->pcc_err_reg);
3528 u64 val64, valt, valr;
3535 val64 = readq(&bar0->pif_rd_swapper_fb);
3536 if (val64 != 0x0123456789ABCDEFULL) {
3547 val64 = readq(&bar0->pif_rd_swapper_fb);
3548 if (val64 == 0x0123456789ABCDEFULL)
3555 dev->name, (unsigned long long)val64);
3565 val64 = readq(&bar0->xmsi_address);
3567 if (val64 != valt) {
3579 val64 = readq(&bar0->xmsi_address);
3580 if (val64 == valt)
3585 unsigned long long x = val64;
3591 val64 = readq(&bar0->swapper_ctrl);
3592 val64 &= 0xFFFF000000000000ULL;
3599 val64 |= (SWAPPER_CTRL_TXP_FE |
3611 val64 |= SWAPPER_CTRL_XMSI_SE;
3612 writeq(val64, &bar0->swapper_ctrl);
3619 val64 |= (SWAPPER_CTRL_TXP_FE |
3635 val64 |= SWAPPER_CTRL_XMSI_SE;
3636 writeq(val64, &bar0->swapper_ctrl);
3638 val64 = readq(&bar0->swapper_ctrl);
3644 val64 = readq(&bar0->pif_rd_swapper_fb);
3645 if (val64 != 0x0123456789ABCDEFULL) {
3649 dev->name, (unsigned long long)val64);
3659 u64 val64;
3663 val64 = readq(&bar0->xmsi_access);
3664 if (!(val64 & s2BIT(15)))
3680 u64 val64;
3690 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3691 writeq(val64, &bar0->xmsi_access);
3701 u64 val64, addr, data;
3710 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3711 writeq(val64, &bar0->xmsi_access);
3827 u64 val64, saved64;
3840 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3841 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3842 val64 |= SCHED_INT_CTRL_TIMER_EN;
3843 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3844 writeq(val64, &bar0->scheduled_int_ctrl);
4012 register u64 val64;
4155 val64 = fifo->list_info[put_off].list_phy_addr;
4156 writeq(val64, &tx_fifo->TxDL_Pointer);
4158 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4161 val64 |= TX_FIFO_SPECIAL_FUNC;
4163 writeq(val64, &tx_fifo->List_Control);
4272 u64 val64;
4274 val64 = readq(&bar0->pic_int_status);
4275 if (val64 & PIC_INT_GPIO) {
4276 val64 = readq(&bar0->gpio_int_reg);
4277 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4278 (val64 & GPIO_INT_REG_LINK_UP)) {
4283 val64 |= GPIO_INT_REG_LINK_DOWN;
4284 val64 |= GPIO_INT_REG_LINK_UP;
4285 writeq(val64, &bar0->gpio_int_reg);
4286 val64 = readq(&bar0->gpio_int_mask);
4287 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4289 writeq(val64, &bar0->gpio_int_mask);
4290 } else if (val64 & GPIO_INT_REG_LINK_UP) {
4291 val64 = readq(&bar0->adapter_status);
4293 val64 = readq(&bar0->adapter_control);
4294 val64 |= ADAPTER_CNTL_EN;
4295 writeq(val64, &bar0->adapter_control);
4296 val64 |= ADAPTER_LED_ON;
4297 writeq(val64, &bar0->adapter_control);
4306 val64 = readq(&bar0->gpio_int_mask);
4307 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4308 val64 |= GPIO_INT_MASK_LINK_UP;
4309 writeq(val64, &bar0->gpio_int_mask);
4311 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4312 val64 = readq(&bar0->adapter_status);
4315 val64 = readq(&bar0->gpio_int_mask);
4316 val64 &= ~GPIO_INT_MASK_LINK_UP;
4317 val64 |= GPIO_INT_MASK_LINK_DOWN;
4318 writeq(val64, &bar0->gpio_int_mask);
4321 val64 = readq(&bar0->adapter_control);
4322 val64 = val64 & (~ADAPTER_LED_ON);
4323 writeq(val64, &bar0->adapter_control);
4326 val64 = readq(&bar0->gpio_int_mask);
4342 u64 val64;
4343 val64 = readq(addr);
4344 if (val64 & value) {
4345 writeq(val64, addr);
4366 u64 temp64 = 0, val64 = 0;
4393 val64 = readq(&bar0->mac_rmac_err_reg);
4394 writeq(val64, &bar0->mac_rmac_err_reg);
4395 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4411 val64 = readq(&bar0->ring_bump_counter1);
4413 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4418 val64 = readq(&bar0->ring_bump_counter2);
4420 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4426 val64 = readq(&bar0->txdma_int_status);
4428 if (val64 & TXDMA_PFC_INT) {
4441 if (val64 & TXDMA_TDA_INT) {
4453 if (val64 & TXDMA_PCC_INT) {
4468 if (val64 & TXDMA_TTI_INT) {
4479 if (val64 & TXDMA_LSO_INT) {
4491 if (val64 & TXDMA_TPA_INT) {
4502 if (val64 & TXDMA_SM_INT) {
4509 val64 = readq(&bar0->mac_int_status);
4510 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4522 val64 = readq(&bar0->xgxs_int_status);
4523 if (val64 & XGXS_INT_STATUS_TXGXS) {
4533 val64 = readq(&bar0->rxdma_int_status);
4534 if (val64 & RXDMA_INT_RC_INT_M) {
4559 if (val64 & RXDMA_INT_RPA_INT_M) {
4569 if (val64 & RXDMA_INT_RDA_INT_M) {
4586 if (val64 & RXDMA_INT_RTI_INT_M) {
4596 val64 = readq(&bar0->mac_int_status);
4597 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4609 val64 = readq(&bar0->xgxs_int_status);
4610 if (val64 & XGXS_INT_STATUS_RXGXS) {
4617 val64 = readq(&bar0->mc_int_status);
4618 if (val64 & MC_INT_STATUS_MC_INT) {
4625 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4626 writeq(val64, &bar0->mc_err_reg);
4627 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4633 if (val64 &
4765 u64 val64;
4770 val64 = SET_UPDT_CLICKS(10) |
4772 writeq(val64, &bar0->stat_cfg);
4775 val64 = readq(&bar0->stat_cfg);
4776 if (!(val64 & s2BIT(0)))
4893 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4905 val64 = RMAC_ADDR_CMD_MEM_WE |
4908 writeq(val64, &bar0->rmac_addr_cmd_mem);
4922 val64 = RMAC_ADDR_CMD_MEM_WE |
4925 writeq(val64, &bar0->rmac_addr_cmd_mem);
4938 val64 = readq(&bar0->mac_cfg);
4939 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4942 writel((u32)val64, add);
4944 writel((u32) (val64 >> 32), (add + 4));
4947 val64 = readq(&bar0->rx_pa_cfg);
4948 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4949 writeq(val64, &bar0->rx_pa_cfg);
4953 val64 = readq(&bar0->mac_cfg);
4960 val64 = readq(&bar0->mac_cfg);
4961 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4964 writel((u32)val64, add);
4966 writel((u32) (val64 >> 32), (add + 4));
4969 val64 = readq(&bar0->rx_pa_cfg);
4970 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
4971 writeq(val64, &bar0->rx_pa_cfg);
4975 val64 = readq(&bar0->mac_cfg);
5000 val64 = RMAC_ADDR_CMD_MEM_WE |
5004 writeq(val64, &bar0->rmac_addr_cmd_mem);
5030 val64 = RMAC_ADDR_CMD_MEM_WE |
5034 writeq(val64, &bar0->rmac_addr_cmd_mem);
5126 u64 val64;
5132 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5134 writeq(val64, &bar0->rmac_addr_cmd_mem);
5172 u64 tmp64, val64;
5176 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5178 writeq(val64, &bar0->rmac_addr_cmd_mem);
5387 u64 val64;
5391 val64 = readq(&bar0->gpio_control);
5393 val64 |= GPIO_CTRL_GPIO_0;
5395 val64 &= ~GPIO_CTRL_GPIO_0;
5397 writeq(val64, &bar0->gpio_control);
5399 val64 = readq(&bar0->adapter_control);
5401 val64 |= ADAPTER_LED_ON;
5403 val64 &= ~ADAPTER_LED_ON;
5405 writeq(val64, &bar0->adapter_control);
5430 u64 val64 = readq(&bar0->adapter_control);
5431 if (!(val64 & ADAPTER_CNTL_EN)) {
5500 u64 val64;
5504 val64 = readq(&bar0->rmac_pause_cfg);
5505 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5507 if (val64 & RMAC_PAUSE_RX_ENABLE)
5526 u64 val64;
5530 val64 = readq(&bar0->rmac_pause_cfg);
5532 val64 |= RMAC_PAUSE_GEN_ENABLE;
5534 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5536 val64 |= RMAC_PAUSE_RX_ENABLE;
5538 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5539 writeq(val64, &bar0->rmac_pause_cfg);
5563 u64 val64;
5567 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5572 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5575 val64 = readq(&bar0->i2c_control);
5576 if (I2C_CONTROL_CNTL_END(val64)) {
5577 *data = I2C_CONTROL_GET_DATA(val64);
5587 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5590 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5591 val64 |= SPI_CONTROL_REQ;
5592 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5594 val64 = readq(&bar0->spi_control);
5595 if (val64 & SPI_CONTROL_NACK) {
5598 } else if (val64 & SPI_CONTROL_DONE) {
5629 u64 val64;
5633 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5638 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5641 val64 = readq(&bar0->i2c_control);
5642 if (I2C_CONTROL_CNTL_END(val64)) {
5643 if (!(val64 & I2C_CONTROL_NACK))
5656 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5659 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5660 val64 |= SPI_CONTROL_REQ;
5661 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5663 val64 = readq(&bar0->spi_control);
5664 if (val64 & SPI_CONTROL_NACK) {
5667 } else if (val64 & SPI_CONTROL_DONE) {
5850 u64 val64 = 0, exp_val;
5853 val64 = readq(&bar0->pif_rd_swapper_fb);
5854 if (val64 != 0x123456789abcdefULL) {
5859 val64 = readq(&bar0->rmac_pause_cfg);
5860 if (val64 != 0xc000ffff00000000ULL) {
5865 val64 = readq(&bar0->rx_queue_cfg);
5870 if (val64 != exp_val) {
5875 val64 = readq(&bar0->xgxs_efifo_cfg);
5876 if (val64 != 0x000000001923141EULL) {
5881 val64 = 0x5A5A5A5A5A5A5A5AULL;
5882 writeq(val64, &bar0->xmsi_data);
5883 val64 = readq(&bar0->xmsi_data);
5884 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5889 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5890 writeq(val64, &bar0->xmsi_data);
5891 val64 = readq(&bar0->xmsi_data);
5892 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
6055 u64 val64;
6057 val64 = readq(&bar0->adapter_status);
6058 if (!(LINK_IS_UP(val64)))
6082 u64 val64;
6085 val64 = readq(&bar0->adapter_control);
6086 val64 &= ~ADAPTER_ECC_EN;
6087 writeq(val64, &bar0->adapter_control);
6089 val64 = readq(&bar0->mc_rldram_test_ctrl);
6090 val64 |= MC_RLDRAM_TEST_MODE;
6091 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6093 val64 = readq(&bar0->mc_rldram_mrs);
6094 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6095 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6097 val64 |= MC_RLDRAM_MRS_ENABLE;
6098 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6101 val64 = 0x55555555aaaa0000ULL;
6103 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6104 writeq(val64, &bar0->mc_rldram_test_d0);
6106 val64 = 0xaaaa5a5555550000ULL;
6108 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6109 writeq(val64, &bar0->mc_rldram_test_d1);
6111 val64 = 0x55aaaaaaaa5a0000ULL;
6113 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6114 writeq(val64, &bar0->mc_rldram_test_d2);
6116 val64 = (u64) (0x0000003ffffe0100ULL);
6117 writeq(val64, &bar0->mc_rldram_test_add);
6119 val64 = MC_RLDRAM_TEST_MODE |
6122 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6125 val64 = readq(&bar0->mc_rldram_test_ctrl);
6126 if (val64 & MC_RLDRAM_TEST_DONE)
6134 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6135 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6138 val64 = readq(&bar0->mc_rldram_test_ctrl);
6139 if (val64 & MC_RLDRAM_TEST_DONE)
6147 val64 = readq(&bar0->mc_rldram_test_ctrl);
6148 if (!(val64 & MC_RLDRAM_TEST_PASS))
6653 u64 val64 = new_mtu;
6655 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6673 register u64 val64;
6695 val64 = readq(&bar0->adapter_status);
6696 if (LINK_IS_UP(val64)) {
6699 val64 = readq(&bar0->adapter_control);
6700 val64 |= ADAPTER_CNTL_EN;
6701 writeq(val64, &bar0->adapter_control);
6704 val64 = readq(&bar0->gpio_control);
6705 val64 |= GPIO_CTRL_GPIO_0;
6706 writeq(val64, &bar0->gpio_control);
6707 val64 = readq(&bar0->gpio_control);
6709 val64 |= ADAPTER_LED_ON;
6710 writeq(val64, &bar0->adapter_control);
6720 val64 = readq(&bar0->adapter_control);
6721 val64 |= ADAPTER_LED_ON;
6722 writeq(val64, &bar0->adapter_control);
6727 val64 = readq(&bar0->gpio_control);
6728 val64 &= ~GPIO_CTRL_GPIO_0;
6729 writeq(val64, &bar0->gpio_control);
6730 val64 = readq(&bar0->gpio_control);
6733 val64 = readq(&bar0->adapter_control);
6734 val64 = val64 & (~ADAPTER_LED_ON);
6735 writeq(val64, &bar0->adapter_control);
7015 register u64 val64 = 0;
7059 val64 = readq(&bar0->adapter_status);
7070 (unsigned long long)val64);
7609 register u64 val64 = 0;
7614 val64 = RTS_DS_MEM_DATA(ring);
7615 writeq(val64, &bar0->rts_ds_mem_data);
7617 val64 = RTS_DS_MEM_CTRL_WE |
7621 writeq(val64, &bar0->rts_ds_mem_ctrl);
7666 u64 val64 = 0, tmp64 = 0;
7933 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7935 writeq(val64, &bar0->rmac_addr_cmd_mem);
8001 val64 = readq(&bar0->gpio_control);
8002 val64 |= 0x0000800000000000ULL;
8003 writeq(val64, &bar0->gpio_control);
8004 val64 = 0x0411040400000000ULL;
8005 writeq(val64, (void __iomem *)bar0 + 0x2700);
8006 val64 = readq(&bar0->gpio_control);