microchip/sparx5/sparx5_vcap_impl.c

263 /* Initializing VCAP rule data area */
282 static bool sparx5_vcap_is0_is_first_chain(struct vcap_rule *rule)
284 	return (rule->vcap_chain_id >= SPARX5_VCAP_CID_IS0_L0 &&
285 		rule->vcap_chain_id < SPARX5_VCAP_CID_IS0_L1) ||
286 		((rule->vcap_chain_id >= SPARX5_VCAP_CID_IS0_L2 &&
287 		  rule->vcap_chain_id < SPARX5_VCAP_CID_IS0_L3)) ||
288 		((rule->vcap_chain_id >= SPARX5_VCAP_CID_IS0_L4 &&
289 		  rule->vcap_chain_id < SPARX5_VCAP_CID_IS0_L5));
293 static bool sparx5_vcap_is2_is_first_chain(struct vcap_rule *rule)
295 	return (rule->vcap_chain_id >= SPARX5_VCAP_CID_IS2_L0 &&
296 		rule->vcap_chain_id < SPARX5_VCAP_CID_IS2_L1) ||
297 		((rule->vcap_chain_id >= SPARX5_VCAP_CID_IS2_L2 &&
298 		  rule->vcap_chain_id < SPARX5_VCAP_CID_IS2_L3));
301 static bool sparx5_vcap_es2_is_first_chain(struct vcap_rule *rule)
303 	return (rule->vcap_chain_id >= SPARX5_VCAP_CID_ES2_L0 &&
304 		rule->vcap_chain_id < SPARX5_VCAP_CID_ES2_L1);
307 /* Set the narrow range ingress port mask on a rule */
308 static void sparx5_vcap_add_ingress_range_port_mask(struct vcap_rule *rule,
318 	vcap_rule_add_key_u32(rule, VCAP_KF_IF_IGR_PORT_MASK_SEL, 0, 0xf);
319 	vcap_rule_add_key_u32(rule, VCAP_KF_IF_IGR_PORT_MASK_RNG, range, 0xf);
320 	vcap_rule_add_key_u32(rule, VCAP_KF_IF_IGR_PORT_MASK, 0, port_mask);
323 /* Set the wide range ingress port mask on a rule */
324 static void sparx5_vcap_add_wide_port_mask(struct vcap_rule *rule,
336 	vcap_rule_add_key_u72(rule, VCAP_KF_IF_IGR_PORT_MASK, &port_mask);
339 static void sparx5_vcap_add_egress_range_port_mask(struct vcap_rule *rule,
356 	vcap_rule_add_key_u32(rule, VCAP_KF_IF_EGR_PORT_MASK_RNG, range, 0xf);
357 	vcap_rule_add_key_u32(rule, VCAP_KF_IF_EGR_PORT_MASK, 0, port_mask);
762 			    struct vcap_rule *rule,
780 		lookup = sparx5_vcap_is0_cid_to_lookup(rule->vcap_chain_id);
785 		lookup = sparx5_vcap_is2_cid_to_lookup(rule->vcap_chain_id);
793 		lookup = sparx5_vcap_es2_cid_to_lookup(rule->vcap_chain_id);
818 						   struct vcap_rule *rule)
824 	field = vcap_lookup_keyfield(rule, VCAP_KF_IF_IGR_PORT_MASK);
826 		sparx5_vcap_add_wide_port_mask(rule, ndev);
828 		sparx5_vcap_add_ingress_range_port_mask(rule, ndev);
832 		       sparx5_vcap_keyset_name(ndev, rule->keyset));
835 		is_first = sparx5_vcap_is0_is_first_chain(rule);
837 		is_first = sparx5_vcap_is2_is_first_chain(rule);
841 		vcap_rule_add_key_bit(rule, VCAP_KF_LOOKUP_FIRST_IS,
844 		vcap_rule_add_key_bit(rule, VCAP_KF_LOOKUP_FIRST_IS,
850 					       struct vcap_rule *rule)
854 	vcap_rule_add_key_u32(rule, VCAP_KF_IF_EGR_PORT_NO, port->portno, ~0);
856 	vcap_rule_add_key_u32(rule, VCAP_KF_8021Q_TPID, SPX5_TPID_SEL_UNTAGGED,
862 					       struct vcap_rule *rule)
868 	field = vcap_lookup_keyfield(rule, VCAP_KF_IF_EGR_PORT_MASK);
870 		sparx5_vcap_add_egress_range_port_mask(rule, ndev);
873 	is_first = sparx5_vcap_es2_is_first_chain(rule);
876 		vcap_rule_add_key_bit(rule, VCAP_KF_LOOKUP_FIRST_IS,
879 		vcap_rule_add_key_bit(rule, VCAP_KF_LOOKUP_FIRST_IS,
883 /* API callback used for adding default fields to a rule */
886 					   struct vcap_rule *rule)
894 		sparx5_vcap_ingress_add_default_fields(ndev, admin, rule);
897 		sparx5_vcap_es0_add_default_fields(ndev, admin, rule);
900 		sparx5_vcap_es2_add_default_fields(ndev, admin, rule);
1951 /* Allocate a vcap instance with a rule list and a cache area */