Lines Matching refs:mlxsw_sp
178 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
189 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
199 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
206 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
209 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
214 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
218 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
224 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
229 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
232 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
307 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
314 return mlxsw_sp->ptp_ops->txhdr_construct(mlxsw_core,
348 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
358 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
363 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
368 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
371 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
378 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
384 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
390 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
395 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
400 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
402 eth_hw_addr_gen(mlxsw_sp_port->dev, mlxsw_sp->base_mac,
410 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
415 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
425 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
433 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
436 static int mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp,
442 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
447 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
451 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
457 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
466 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
473 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
481 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spfsr), spfsr_pl);
508 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
518 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spevet), spevet_pl);
524 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
536 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
542 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
546 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
578 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
582 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
586 mlxsw_sp_port_module_info_parse(struct mlxsw_sp *mlxsw_sp,
604 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: width value is not power of 2\n",
611 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple modules\n",
616 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple slot indexes\n",
623 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are different\n",
628 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are not sequential\n",
643 mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, u16 local_port,
650 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
653 return mlxsw_sp_port_module_info_parse(mlxsw_sp, local_port,
658 mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u16 local_port,
664 mlxsw_env_module_port_map(mlxsw_sp->core, port_mapping->slot_index,
676 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
682 mlxsw_env_module_port_unmap(mlxsw_sp->core, port_mapping->slot_index,
687 static void mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u16 local_port,
694 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
695 mlxsw_env_module_port_unmap(mlxsw_sp->core, slot_index, module);
701 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
704 err = mlxsw_env_module_port_up(mlxsw_sp->core,
716 mlxsw_env_module_port_down(mlxsw_sp->core,
725 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
729 mlxsw_env_module_port_down(mlxsw_sp->core,
739 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
750 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
758 err = mlxsw_sp_txhdr_handle(mlxsw_sp->core, mlxsw_sp_port, skb,
771 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
893 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
896 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1022 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1032 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1226 err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pplr),
1291 err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port,
1308 err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_get(mlxsw_sp_port,
1323 mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, &config);
1361 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1368 ops = mlxsw_sp->port_type_speed_ops;
1373 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
1375 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1379 ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, ð_proto_cap,
1382 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
1385 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1391 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1396 port_type_speed_ops = mlxsw_sp->port_type_speed_ops;
1397 port_type_speed_ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl,
1400 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1403 port_type_speed_ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, NULL, NULL,
1405 *speed = port_type_speed_ops->from_ptys_speed(mlxsw_sp, eth_proto_oper);
1413 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1421 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1428 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1436 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1443 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1451 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1457 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1462 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
1554 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1558 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
1563 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1569 err = mlxsw_env_module_overheat_counter_get(mlxsw_sp->core, slot_index,
1583 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1588 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvc), spvc_pl);
1591 static int mlxsw_sp_port_label_info_get(struct mlxsw_sp *mlxsw_sp,
1600 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pllp), pllp_pl);
1608 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u16 local_port,
1622 err = mlxsw_sp_port_module_map(mlxsw_sp, local_port, port_mapping);
1624 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
1629 err = mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 0);
1631 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
1636 err = mlxsw_sp_port_label_info_get(mlxsw_sp, local_port, &port_number,
1639 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get port label information\n",
1645 err = mlxsw_core_port_init(mlxsw_sp->core, local_port, slot_index,
1647 splittable, lanes, mlxsw_sp->base_mac,
1648 sizeof(mlxsw_sp->base_mac));
1650 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
1660 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
1661 dev_net_set(dev, mlxsw_sp_net(mlxsw_sp));
1663 mlxsw_core_port_netdev_link(mlxsw_sp->core, local_port,
1666 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1689 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
1710 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1717 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
1722 err = mlxsw_sp->port_type_speed_ops->ptys_max_speed(mlxsw_sp_port,
1725 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum speed\n",
1732 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum MTU\n",
1739 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
1750 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
1757 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
1764 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
1772 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
1779 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
1786 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
1794 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to clear VLAN filter\n",
1801 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n",
1809 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n",
1817 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
1829 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set default VLAN classification\n",
1835 mlxsw_sp->ptp_ops->shaper_work);
1837 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
1841 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set overheat initial value\n",
1848 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
1860 mlxsw_sp->ports[local_port] = NULL;
1889 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
1892 mlxsw_sp_port_swid_set(mlxsw_sp, local_port,
1895 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port,
1901 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u16 local_port)
1903 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
1912 mlxsw_sp->ports[local_port] = NULL;
1923 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
1924 mlxsw_sp_port_swid_set(mlxsw_sp, local_port,
1926 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port, slot_index, module);
1929 static int mlxsw_sp_cpu_port_create(struct mlxsw_sp *mlxsw_sp)
1938 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1941 err = mlxsw_core_cpu_port_init(mlxsw_sp->core,
1943 mlxsw_sp->base_mac,
1944 sizeof(mlxsw_sp->base_mac));
1946 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize core CPU port\n");
1950 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = mlxsw_sp_port;
1958 static void mlxsw_sp_cpu_port_remove(struct mlxsw_sp *mlxsw_sp)
1961 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT];
1963 mlxsw_core_cpu_port_fini(mlxsw_sp->core);
1964 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = NULL;
1973 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u16 local_port)
1977 return mlxsw_sp->ports[local_port] != NULL;
1980 static int mlxsw_sp_port_mapping_event_set(struct mlxsw_sp *mlxsw_sp,
1988 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmecr), pmecr_pl);
2001 struct mlxsw_sp *mlxsw_sp;
2008 mlxsw_sp = container_of(events, struct mlxsw_sp, port_mapping_events);
2009 devlink = priv_to_devlink(mlxsw_sp->core);
2017 err = mlxsw_sp_port_module_info_parse(mlxsw_sp, local_port,
2027 if (!mlxsw_sp_port_created(mlxsw_sp, local_port))
2028 mlxsw_sp_port_create(mlxsw_sp, local_port,
2035 mlxsw_sp->port_mapping[local_port] = port_mapping;
2048 struct mlxsw_sp *mlxsw_sp = priv;
2052 if (WARN_ON_ONCE(!mlxsw_sp_local_port_is_valid(mlxsw_sp, local_port)))
2055 events = &mlxsw_sp->port_mapping_events;
2067 __mlxsw_sp_port_mapping_events_cancel(struct mlxsw_sp *mlxsw_sp)
2072 events = &mlxsw_sp->port_mapping_events;
2082 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2084 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
2088 mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, false);
2090 __mlxsw_sp_port_mapping_events_cancel(mlxsw_sp);
2093 if (mlxsw_sp_port_created(mlxsw_sp, i))
2094 mlxsw_sp_port_remove(mlxsw_sp, i);
2095 mlxsw_sp_cpu_port_remove(mlxsw_sp);
2096 kfree(mlxsw_sp->ports);
2097 mlxsw_sp->ports = NULL;
2105 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2110 if (mlxsw_sp_port_created(mlxsw_sp, i) && selector(priv, i))
2111 mlxsw_sp_port_remove(mlxsw_sp, i);
2114 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
2116 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
2124 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
2125 if (!mlxsw_sp->ports)
2128 events = &mlxsw_sp->port_mapping_events;
2134 err = mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, true);
2139 err = mlxsw_sp_cpu_port_create(mlxsw_sp);
2144 port_mapping = &mlxsw_sp->port_mapping[i];
2147 err = mlxsw_sp_port_create(mlxsw_sp, i, false, port_mapping);
2155 if (mlxsw_sp_port_created(mlxsw_sp, i))
2156 mlxsw_sp_port_remove(mlxsw_sp, i);
2158 mlxsw_sp_cpu_port_remove(mlxsw_sp);
2162 mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, false);
2164 __mlxsw_sp_port_mapping_events_cancel(mlxsw_sp);
2165 kfree(mlxsw_sp->ports);
2166 mlxsw_sp->ports = NULL;
2170 static int mlxsw_sp_port_module_info_init(struct mlxsw_sp *mlxsw_sp)
2172 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
2177 mlxsw_sp->port_mapping = kcalloc(max_ports,
2180 if (!mlxsw_sp->port_mapping)
2184 port_mapping = &mlxsw_sp->port_mapping[i];
2185 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, port_mapping);
2192 kfree(mlxsw_sp->port_mapping);
2196 static void mlxsw_sp_port_module_info_fini(struct mlxsw_sp *mlxsw_sp)
2198 kfree(mlxsw_sp->port_mapping);
2202 mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp,
2217 err = mlxsw_sp_port_create(mlxsw_sp, s_local_port,
2230 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port))
2231 mlxsw_sp_port_remove(mlxsw_sp, s_local_port);
2236 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
2247 port_mapping = &mlxsw_sp->port_mapping[local_port];
2250 mlxsw_sp_port_create(mlxsw_sp, local_port,
2256 mlxsw_sp_port_get_by_local_port(struct mlxsw_sp *mlxsw_sp, u16 local_port)
2258 if (mlxsw_sp->ports && mlxsw_sp->ports[local_port])
2259 return mlxsw_sp->ports[local_port];
2267 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2275 mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port);
2277 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2309 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port))
2310 mlxsw_sp_port_remove(mlxsw_sp, s_local_port);
2313 err = mlxsw_sp_port_split_create(mlxsw_sp, &port_mapping,
2316 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2323 mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl);
2331 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2338 mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port);
2340 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2367 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port))
2368 mlxsw_sp_port_remove(mlxsw_sp, s_local_port);
2371 mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl);
2388 struct mlxsw_sp *mlxsw_sp = priv;
2395 if (WARN_ON_ONCE(!mlxsw_sp_local_port_is_valid(mlxsw_sp, local_port)))
2397 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2413 static void mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp *mlxsw_sp,
2431 mlxsw_sp1_ptp_got_timestamp(mlxsw_sp, ingress, local_port,
2440 struct mlxsw_sp *mlxsw_sp = priv;
2442 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, true);
2448 struct mlxsw_sp *mlxsw_sp = priv;
2450 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, false);
2456 struct mlxsw_sp *mlxsw_sp = priv;
2457 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2461 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2493 void mlxsw_sp_ptp_receive(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
2496 mlxsw_sp->ptp_ops->receive(mlxsw_sp, skb, local_port);
2553 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2581 __set_bit(i, mlxsw_sp->trap->policers_usage);
2639 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2645 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_CPU_POLICERS))
2647 max_policers = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_CPU_POLICERS);
2653 mlxsw_sp->trap = trap;
2655 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
2659 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
2663 err = mlxsw_core_traps_register(mlxsw_sp->core, mlxsw_sp_listener,
2665 mlxsw_sp);
2669 err = mlxsw_core_traps_register(mlxsw_sp->core, mlxsw_sp->listeners,
2670 mlxsw_sp->listeners_count, mlxsw_sp);
2677 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp_listener,
2679 mlxsw_sp);
2687 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2689 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp->listeners,
2690 mlxsw_sp->listeners_count,
2691 mlxsw_sp);
2692 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp_listener,
2693 ARRAY_SIZE(mlxsw_sp_listener), mlxsw_sp);
2694 kfree(mlxsw_sp->trap);
2697 static int mlxsw_sp_lag_pgt_init(struct mlxsw_sp *mlxsw_sp)
2702 if (mlxsw_core_lag_mode(mlxsw_sp->core) !=
2710 err = mlxsw_sp_pgt_mid_alloc_range(mlxsw_sp, &mlxsw_sp->lag_pgt_base,
2711 mlxsw_sp->max_lag * 8);
2714 if (WARN_ON_ONCE(mlxsw_sp->lag_pgt_base % 8)) {
2719 mlxsw_reg_sgcr_pack(sgcr_pl, mlxsw_sp->lag_pgt_base);
2720 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sgcr), sgcr_pl);
2727 mlxsw_sp_pgt_mid_free_range(mlxsw_sp, mlxsw_sp->lag_pgt_base,
2728 mlxsw_sp->max_lag * 8);
2732 static void mlxsw_sp_lag_pgt_fini(struct mlxsw_sp *mlxsw_sp)
2734 if (mlxsw_core_lag_mode(mlxsw_sp->core) !=
2738 mlxsw_sp_pgt_mid_free_range(mlxsw_sp, mlxsw_sp->lag_pgt_base,
2739 mlxsw_sp->max_lag * 8);
2750 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2756 seed = jhash(mlxsw_sp->base_mac, sizeof(mlxsw_sp->base_mac),
2767 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2771 err = mlxsw_core_max_lag(mlxsw_sp->core, &mlxsw_sp->max_lag);
2775 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
2778 err = mlxsw_sp_lag_pgt_init(mlxsw_sp);
2782 mlxsw_sp->lags = kcalloc(mlxsw_sp->max_lag, sizeof(struct mlxsw_sp_lag),
2784 if (!mlxsw_sp->lags) {
2792 mlxsw_sp_lag_pgt_fini(mlxsw_sp);
2796 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
2798 mlxsw_sp_lag_pgt_fini(mlxsw_sp);
2799 kfree(mlxsw_sp->lags);
2879 mlxsw_sp_sample_trigger_params_lookup(struct mlxsw_sp *mlxsw_sp,
2886 trigger_node = rhashtable_lookup(&mlxsw_sp->sample_trigger_ht, &key,
2895 mlxsw_sp_sample_trigger_node_init(struct mlxsw_sp *mlxsw_sp,
2910 err = rhashtable_insert_fast(&mlxsw_sp->sample_trigger_ht,
2924 mlxsw_sp_sample_trigger_node_fini(struct mlxsw_sp *mlxsw_sp,
2927 rhashtable_remove_fast(&mlxsw_sp->sample_trigger_ht,
2934 mlxsw_sp_sample_trigger_params_set(struct mlxsw_sp *mlxsw_sp,
2946 trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht,
2950 return mlxsw_sp_sample_trigger_node_init(mlxsw_sp, &key,
2972 mlxsw_sp_sample_trigger_params_unset(struct mlxsw_sp *mlxsw_sp,
2982 trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht,
2991 mlxsw_sp_sample_trigger_node_fini(mlxsw_sp, trigger_node);
3001 static void mlxsw_sp_parsing_init(struct mlxsw_sp *mlxsw_sp)
3003 refcount_set(&mlxsw_sp->parsing.parsing_depth_ref, 0);
3004 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH;
3005 mlxsw_sp->parsing.vxlan_udp_dport = MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT;
3006 mutex_init(&mlxsw_sp->parsing.lock);
3009 static void mlxsw_sp_parsing_fini(struct mlxsw_sp *mlxsw_sp)
3011 mutex_destroy(&mlxsw_sp->parsing.lock);
3012 WARN_ON_ONCE(refcount_read(&mlxsw_sp->parsing.parsing_depth_ref));
3030 mlxsw_sp_ipv6_addr_init(struct mlxsw_sp *mlxsw_sp, const struct in6_addr *addr6,
3037 err = mlxsw_sp_kvdl_alloc(mlxsw_sp,
3044 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(rips), rips_pl);
3058 err = rhashtable_insert_fast(&mlxsw_sp->ipv6_addr_ht,
3070 mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1,
3075 static void mlxsw_sp_ipv6_addr_fini(struct mlxsw_sp *mlxsw_sp,
3080 rhashtable_remove_fast(&mlxsw_sp->ipv6_addr_ht, &node->ht_node,
3083 mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1,
3087 int mlxsw_sp_ipv6_addr_kvdl_index_get(struct mlxsw_sp *mlxsw_sp,
3094 mutex_lock(&mlxsw_sp->ipv6_addr_ht_lock);
3095 node = rhashtable_lookup_fast(&mlxsw_sp->ipv6_addr_ht, addr6,
3103 err = mlxsw_sp_ipv6_addr_init(mlxsw_sp, addr6, p_kvdl_index);
3106 mutex_unlock(&mlxsw_sp->ipv6_addr_ht_lock);
3111 mlxsw_sp_ipv6_addr_put(struct mlxsw_sp *mlxsw_sp, const struct in6_addr *addr6)
3115 mutex_lock(&mlxsw_sp->ipv6_addr_ht_lock);
3116 node = rhashtable_lookup_fast(&mlxsw_sp->ipv6_addr_ht, addr6,
3124 mlxsw_sp_ipv6_addr_fini(mlxsw_sp, node);
3127 mutex_unlock(&mlxsw_sp->ipv6_addr_ht_lock);
3130 static int mlxsw_sp_ipv6_addr_ht_init(struct mlxsw_sp *mlxsw_sp)
3134 err = rhashtable_init(&mlxsw_sp->ipv6_addr_ht,
3139 mutex_init(&mlxsw_sp->ipv6_addr_ht_lock);
3143 static void mlxsw_sp_ipv6_addr_ht_fini(struct mlxsw_sp *mlxsw_sp)
3145 mutex_destroy(&mlxsw_sp->ipv6_addr_ht_lock);
3146 rhashtable_destroy(&mlxsw_sp->ipv6_addr_ht);
3153 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3156 mlxsw_sp->core = mlxsw_core;
3157 mlxsw_sp->bus_info = mlxsw_bus_info;
3159 mlxsw_sp_parsing_init(mlxsw_sp);
3161 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3163 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3167 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3169 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3173 err = mlxsw_sp_pgt_init(mlxsw_sp);
3175 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PGT\n");
3182 err = mlxsw_sp_lag_init(mlxsw_sp);
3184 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3188 err = mlxsw_sp->fid_core_ops->init(mlxsw_sp);
3190 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
3194 err = mlxsw_sp_policers_init(mlxsw_sp);
3196 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize policers\n");
3200 err = mlxsw_sp_traps_init(mlxsw_sp);
3202 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3206 err = mlxsw_sp_devlink_traps_init(mlxsw_sp);
3208 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize devlink traps\n");
3212 err = mlxsw_sp_buffers_init(mlxsw_sp);
3214 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3221 err = mlxsw_sp_span_init(mlxsw_sp);
3223 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3227 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3229 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3233 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3235 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3239 err = mlxsw_sp_afa_init(mlxsw_sp);
3241 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3245 err = mlxsw_sp_ipv6_addr_ht_init(mlxsw_sp);
3247 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize hash table for IPv6 addresses\n");
3251 err = mlxsw_sp_nve_init(mlxsw_sp);
3253 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n");
3257 err = mlxsw_sp_port_range_init(mlxsw_sp);
3259 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize port ranges\n");
3263 err = mlxsw_sp_acl_init(mlxsw_sp);
3265 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3269 err = mlxsw_sp_router_init(mlxsw_sp, extack);
3271 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3275 if (mlxsw_sp->bus_info->read_clock_capable) {
3277 mlxsw_sp->clock =
3278 mlxsw_sp->ptp_ops->clock_init(mlxsw_sp,
3279 mlxsw_sp->bus_info->dev);
3280 if (IS_ERR(mlxsw_sp->clock)) {
3281 err = PTR_ERR(mlxsw_sp->clock);
3282 dev_err(mlxsw_sp->bus_info->dev, "Failed to init ptp clock\n");
3287 if (mlxsw_sp->clock) {
3289 mlxsw_sp->ptp_state = mlxsw_sp->ptp_ops->init(mlxsw_sp);
3290 if (IS_ERR(mlxsw_sp->ptp_state)) {
3291 err = PTR_ERR(mlxsw_sp->ptp_state);
3292 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PTP\n");
3300 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3301 err = register_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
3302 &mlxsw_sp->netdevice_nb);
3304 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3308 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3310 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3314 err = mlxsw_sp_port_module_info_init(mlxsw_sp);
3316 dev_err(mlxsw_sp->bus_info->dev, "Failed to init port module info\n");
3320 err = rhashtable_init(&mlxsw_sp->sample_trigger_ht,
3323 dev_err(mlxsw_sp->bus_info->dev, "Failed to init sampling trigger hashtable\n");
3327 err = mlxsw_sp_ports_create(mlxsw_sp);
3329 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3336 rhashtable_destroy(&mlxsw_sp->sample_trigger_ht);
3338 mlxsw_sp_port_module_info_fini(mlxsw_sp);
3340 mlxsw_sp_dpipe_fini(mlxsw_sp);
3342 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
3343 &mlxsw_sp->netdevice_nb);
3345 if (mlxsw_sp->clock)
3346 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
3348 if (mlxsw_sp->clock)
3349 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
3351 mlxsw_sp_router_fini(mlxsw_sp);
3353 mlxsw_sp_acl_fini(mlxsw_sp);
3355 mlxsw_sp_port_range_fini(mlxsw_sp);
3357 mlxsw_sp_nve_fini(mlxsw_sp);
3359 mlxsw_sp_ipv6_addr_ht_fini(mlxsw_sp);
3361 mlxsw_sp_afa_fini(mlxsw_sp);
3363 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3365 mlxsw_sp_switchdev_fini(mlxsw_sp);
3367 mlxsw_sp_span_fini(mlxsw_sp);
3369 mlxsw_sp_buffers_fini(mlxsw_sp);
3371 mlxsw_sp_devlink_traps_fini(mlxsw_sp);
3373 mlxsw_sp_traps_fini(mlxsw_sp);
3375 mlxsw_sp_policers_fini(mlxsw_sp);
3377 mlxsw_sp->fid_core_ops->fini(mlxsw_sp);
3379 mlxsw_sp_lag_fini(mlxsw_sp);
3381 mlxsw_sp_pgt_fini(mlxsw_sp);
3383 mlxsw_sp_kvdl_fini(mlxsw_sp);
3384 mlxsw_sp_parsing_fini(mlxsw_sp);
3392 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3394 mlxsw_sp->switchdev_ops = &mlxsw_sp1_switchdev_ops;
3395 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
3396 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
3397 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
3398 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
3399 mlxsw_sp->acl_rulei_ops = &mlxsw_sp1_acl_rulei_ops;
3400 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
3401 mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr;
3402 mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask;
3403 mlxsw_sp->sb_vals = &mlxsw_sp1_sb_vals;
3404 mlxsw_sp->sb_ops = &mlxsw_sp1_sb_ops;
3405 mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops;
3406 mlxsw_sp->ptp_ops = &mlxsw_sp1_ptp_ops;
3407 mlxsw_sp->span_ops = &mlxsw_sp1_span_ops;
3408 mlxsw_sp->policer_core_ops = &mlxsw_sp1_policer_core_ops;
3409 mlxsw_sp->trap_ops = &mlxsw_sp1_trap_ops;
3410 mlxsw_sp->mall_ops = &mlxsw_sp1_mall_ops;
3411 mlxsw_sp->router_ops = &mlxsw_sp1_router_ops;
3412 mlxsw_sp->listeners = mlxsw_sp1_listener;
3413 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp1_listener);
3414 mlxsw_sp->fid_core_ops = &mlxsw_sp1_fid_core_ops;
3415 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1;
3416 mlxsw_sp->pgt_smpe_index_valid = true;
3425 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3427 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops;
3428 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
3429 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
3430 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
3431 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
3432 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops;
3433 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
3434 mlxsw_sp->acl_bf_ops = &mlxsw_sp2_acl_bf_ops;
3435 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
3436 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
3437 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
3438 mlxsw_sp->sb_ops = &mlxsw_sp2_sb_ops;
3439 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
3440 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
3441 mlxsw_sp->span_ops = &mlxsw_sp2_span_ops;
3442 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops;
3443 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops;
3444 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops;
3445 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops;
3446 mlxsw_sp->listeners = mlxsw_sp2_listener;
3447 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener);
3448 mlxsw_sp->fid_core_ops = &mlxsw_sp2_fid_core_ops;
3449 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2;
3450 mlxsw_sp->pgt_smpe_index_valid = false;
3459 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3461 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops;
3462 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
3463 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
3464 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
3465 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
3466 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops;
3467 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
3468 mlxsw_sp->acl_bf_ops = &mlxsw_sp2_acl_bf_ops;
3469 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
3470 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
3471 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
3472 mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops;
3473 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
3474 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
3475 mlxsw_sp->span_ops = &mlxsw_sp3_span_ops;
3476 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops;
3477 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops;
3478 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops;
3479 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops;
3480 mlxsw_sp->listeners = mlxsw_sp2_listener;
3481 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener);
3482 mlxsw_sp->fid_core_ops = &mlxsw_sp2_fid_core_ops;
3483 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3;
3484 mlxsw_sp->pgt_smpe_index_valid = false;
3493 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3495 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops;
3496 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
3497 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
3498 mlxsw_sp->afk_ops = &mlxsw_sp4_afk_ops;
3499 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
3500 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops;
3501 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
3502 mlxsw_sp->acl_bf_ops = &mlxsw_sp4_acl_bf_ops;
3503 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
3504 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
3505 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
3506 mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops;
3507 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
3508 mlxsw_sp->ptp_ops = &mlxsw_sp4_ptp_ops;
3509 mlxsw_sp->span_ops = &mlxsw_sp3_span_ops;
3510 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops;
3511 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops;
3512 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops;
3513 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops;
3514 mlxsw_sp->listeners = mlxsw_sp2_listener;
3515 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener);
3516 mlxsw_sp->fid_core_ops = &mlxsw_sp2_fid_core_ops;
3517 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4;
3518 mlxsw_sp->pgt_smpe_index_valid = false;
3525 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3527 mlxsw_sp_ports_remove(mlxsw_sp);
3528 rhashtable_destroy(&mlxsw_sp->sample_trigger_ht);
3529 mlxsw_sp_port_module_info_fini(mlxsw_sp);
3530 mlxsw_sp_dpipe_fini(mlxsw_sp);
3531 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
3532 &mlxsw_sp->netdevice_nb);
3533 if (mlxsw_sp->clock) {
3534 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
3535 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
3537 mlxsw_sp_router_fini(mlxsw_sp);
3538 mlxsw_sp_acl_fini(mlxsw_sp);
3539 mlxsw_sp_port_range_fini(mlxsw_sp);
3540 mlxsw_sp_nve_fini(mlxsw_sp);
3541 mlxsw_sp_ipv6_addr_ht_fini(mlxsw_sp);
3542 mlxsw_sp_afa_fini(mlxsw_sp);
3543 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3544 mlxsw_sp_switchdev_fini(mlxsw_sp);
3545 mlxsw_sp_span_fini(mlxsw_sp);
3546 mlxsw_sp_buffers_fini(mlxsw_sp);
3547 mlxsw_sp_devlink_traps_fini(mlxsw_sp);
3548 mlxsw_sp_traps_fini(mlxsw_sp);
3549 mlxsw_sp_policers_fini(mlxsw_sp);
3550 mlxsw_sp->fid_core_ops->fini(mlxsw_sp);
3551 mlxsw_sp_lag_fini(mlxsw_sp);
3552 mlxsw_sp_pgt_fini(mlxsw_sp);
3553 mlxsw_sp_kvdl_fini(mlxsw_sp);
3554 mlxsw_sp_parsing_fini(mlxsw_sp);
3978 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3981 mlxsw_sp->ptp_ops->transmitted(mlxsw_sp, skb, local_port);
3986 .priv_size = sizeof(struct mlxsw_sp),
4023 .priv_size = sizeof(struct mlxsw_sp),
4060 .priv_size = sizeof(struct mlxsw_sp),
4097 .priv_size = sizeof(struct mlxsw_sp),
4162 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
4167 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4185 int mlxsw_sp_parsing_depth_inc(struct mlxsw_sp *mlxsw_sp)
4190 mutex_lock(&mlxsw_sp->parsing.lock);
4192 if (refcount_inc_not_zero(&mlxsw_sp->parsing.parsing_depth_ref))
4196 mlxsw_sp->parsing.vxlan_udp_dport);
4197 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl);
4201 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_INCREASED_PARSING_DEPTH;
4202 refcount_set(&mlxsw_sp->parsing.parsing_depth_ref, 1);
4205 mutex_unlock(&mlxsw_sp->parsing.lock);
4209 void mlxsw_sp_parsing_depth_dec(struct mlxsw_sp *mlxsw_sp)
4213 mutex_lock(&mlxsw_sp->parsing.lock);
4215 if (!refcount_dec_and_test(&mlxsw_sp->parsing.parsing_depth_ref))
4219 mlxsw_sp->parsing.vxlan_udp_dport);
4220 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl);
4221 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH;
4224 mutex_unlock(&mlxsw_sp->parsing.lock);
4227 int mlxsw_sp_parsing_vxlan_udp_dport_set(struct mlxsw_sp *mlxsw_sp,
4233 mutex_lock(&mlxsw_sp->parsing.lock);
4235 mlxsw_reg_mprs_pack(mprs_pl, mlxsw_sp->parsing.parsing_depth,
4237 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl);
4241 mlxsw_sp->parsing.vxlan_udp_dport = be16_to_cpu(udp_dport);
4244 mutex_unlock(&mlxsw_sp->parsing.lock);
4268 mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, struct net_device *lag_dev,
4276 for (i = 0; i < mlxsw_sp->max_lag; i++) {
4277 if (!mlxsw_sp->lags[i].dev)
4281 if (i == mlxsw_sp->max_lag) {
4289 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4293 lag = &mlxsw_sp->lags[lag_id];
4302 mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_lag *lag)
4309 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4315 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4320 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4326 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4331 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4337 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4342 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4348 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4353 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4357 mlxsw_sp_lag_find(struct mlxsw_sp *mlxsw_sp, struct net_device *lag_dev)
4361 for (i = 0; i < mlxsw_sp->max_lag; i++) {
4362 if (!mlxsw_sp->lags[i].dev)
4365 if (mlxsw_sp->lags[i].dev == lag_dev)
4366 return &mlxsw_sp->lags[i];
4373 mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, struct net_device *lag_dev,
4378 lag = mlxsw_sp_lag_find(mlxsw_sp, lag_dev);
4384 return mlxsw_sp_lag_create(mlxsw_sp, lag_dev, extack);
4388 mlxsw_sp_lag_put(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_lag *lag)
4393 mlxsw_sp_lag_destroy(mlxsw_sp, lag);
4397 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4409 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4415 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4418 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4512 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4518 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_dev, extack);
4523 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4536 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4555 err = mlxsw_sp_netdevice_enslavement_replay(mlxsw_sp, lag_dev, extack);
4567 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4573 mlxsw_sp_lag_put(mlxsw_sp, lag);
4580 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4586 lag = &mlxsw_sp->lags[lag_id];
4600 mlxsw_sp_lag_put(mlxsw_sp, lag);
4602 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4614 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4619 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4625 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4630 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4688 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4705 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4826 static int __mlxsw_sp_netdevice_event(struct mlxsw_sp *mlxsw_sp,
4830 static int mlxsw_sp_netdevice_validate_uppers(struct mlxsw_sp *mlxsw_sp,
4857 err = __mlxsw_sp_netdevice_event(mlxsw_sp,
4863 err = mlxsw_sp_netdevice_validate_uppers(mlxsw_sp, upper_dev,
4881 struct mlxsw_sp *mlxsw_sp;
4886 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4905 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
4911 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4913 err = mlxsw_sp_netdevice_validate_uppers(mlxsw_sp,
4920 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4989 mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp,
5000 mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp,
5010 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
5078 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(dev);
5081 if (!mlxsw_sp)
5089 mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp, dev);
5120 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5140 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
5146 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
5148 err = mlxsw_sp_netdevice_validate_uppers(mlxsw_sp,
5169 mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp,
5174 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
5204 static int mlxsw_sp_netdevice_bridge_vlan_event(struct mlxsw_sp *mlxsw_sp,
5233 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
5240 static int mlxsw_sp_netdevice_vlan_event(struct mlxsw_sp *mlxsw_sp,
5257 return mlxsw_sp_netdevice_bridge_vlan_event(mlxsw_sp, vlan_dev,
5265 static int mlxsw_sp_netdevice_bridge_event(struct mlxsw_sp *mlxsw_sp,
5309 mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev);
5311 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
5321 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev);
5326 if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER)
5340 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp,
5372 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev,
5380 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
5391 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0,
5401 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
5408 static int __mlxsw_sp_netdevice_event(struct mlxsw_sp *mlxsw_sp,
5417 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
5419 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
5423 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr);
5429 err = mlxsw_sp_netdevice_vlan_event(mlxsw_sp, dev, event, ptr,
5432 err = mlxsw_sp_netdevice_bridge_event(mlxsw_sp, dev, event, ptr,
5443 struct mlxsw_sp *mlxsw_sp;
5446 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
5447 mlxsw_sp_span_respin(mlxsw_sp);
5448 err = __mlxsw_sp_netdevice_event(mlxsw_sp, event, ptr, false);