Lines Matching refs:mbox
293 static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
312 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, cq_num);
313 mlxsw_cmd_mbox_sw2hw_dq_sdq_lp_set(mbox, lp);
314 mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, tclass);
315 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
319 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
322 err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num);
406 static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
423 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, cq_num);
424 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
428 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
431 err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num);
845 static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
860 mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox,
863 mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox,
866 mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM);
867 mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0);
868 mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count));
872 mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr);
874 err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num);
951 static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
972 mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */
973 mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */
974 mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count));
978 mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr);
980 err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num);
1000 int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox,
1043 static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
1087 mlxsw_cmd_mbox_zero(mbox);
1088 err = q_ops->init(mlxsw_pci, mbox, q);
1113 static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
1127 err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops,
1155 static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox)
1169 mlxsw_cmd_mbox_zero(mbox);
1170 err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox);
1174 num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox);
1175 sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox);
1176 num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox);
1177 rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox);
1178 num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox);
1179 cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox);
1180 cqv2_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cqv2_sz_get(mbox);
1181 num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox);
1182 eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox);
1204 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops,
1211 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops,
1218 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops,
1225 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops,
1253 char *mbox, int index,
1260 mbox, index, swid->type);
1265 mbox, index, swid->properties);
1268 mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask);
1292 static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox,
1299 mlxsw_cmd_mbox_zero(mbox);
1303 mbox, 1);
1305 mbox, profile->max_vepa_channels);
1308 mlxsw_cmd_mbox_config_profile_set_max_lag_set(mbox, 1);
1309 mlxsw_cmd_mbox_config_profile_max_lag_set(mbox,
1314 mbox, 1);
1316 mbox, profile->max_mid);
1320 mbox, 1);
1322 mbox, profile->max_pgt);
1326 mbox, 1);
1328 mbox, profile->max_system_port);
1332 mbox, 1);
1334 mbox, profile->max_vlan_groups);
1338 mbox, 1);
1340 mbox, profile->max_regions);
1344 mbox, 1);
1346 mbox, profile->max_flood_tables);
1348 mbox, profile->max_vid_flood_tables);
1350 mbox, profile->max_fid_offset_flood_tables);
1352 mbox, profile->fid_offset_flood_table_size);
1354 mbox, profile->max_fid_flood_tables);
1356 mbox, profile->fid_flood_table_size);
1362 mlxsw_cmd_mbox_config_profile_set_flood_mode_set(mbox, 1);
1363 mlxsw_cmd_mbox_config_profile_flood_mode_set(mbox, flood_mode);
1367 mbox, 1);
1369 mbox, profile->flood_mode);
1377 mbox, 1);
1379 mbox, profile->max_ib_mc);
1383 mbox, 1);
1385 mbox, profile->max_pkey);
1389 mbox, 1);
1391 mbox, profile->ar_sec);
1395 mbox, 1);
1397 mbox, profile->adaptive_routing_group_cap);
1400 mlxsw_cmd_mbox_config_profile_set_ubridge_set(mbox, 1);
1401 mlxsw_cmd_mbox_config_profile_ubridge_set(mbox,
1409 mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set(mbox, 1);
1410 mlxsw_cmd_mbox_config_profile_kvd_linear_size_set(mbox,
1412 mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set(mbox,
1414 mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set(mbox,
1417 mbox, 1);
1418 mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set(mbox,
1423 mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i,
1427 mlxsw_cmd_mbox_config_profile_set_cqe_version_set(mbox, 1);
1428 mlxsw_cmd_mbox_config_profile_cqe_version_set(mbox, 1);
1432 mlxsw_cmd_mbox_config_profile_set_cqe_time_stamp_type_set(mbox,
1434 mlxsw_cmd_mbox_config_profile_cqe_time_stamp_type_set(mbox,
1442 mlxsw_cmd_mbox_config_profile_set_lag_mode_set(mbox, 1);
1443 mlxsw_cmd_mbox_config_profile_lag_mode_set(mbox, lag_mode);
1448 return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox);
1451 static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox)
1456 mlxsw_cmd_mbox_zero(mbox);
1457 err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox);
1460 mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd);
1461 mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid);
1465 static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
1479 mlxsw_cmd_mbox_zero(mbox);
1491 mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr);
1492 mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0); /* 1 page */
1494 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1498 mlxsw_cmd_mbox_zero(mbox);
1503 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1549 struct mlxsw_pci_mem_item *mbox)
1554 mbox->size = MLXSW_CMD_MBOX_SIZE;
1555 mbox->buf = dma_alloc_coherent(&pdev->dev, MLXSW_CMD_MBOX_SIZE,
1556 &mbox->mapaddr, GFP_KERNEL);
1557 if (!mbox->buf) {
1566 struct mlxsw_pci_mem_item *mbox)
1570 dma_free_coherent(&pdev->dev, MLXSW_CMD_MBOX_SIZE, mbox->buf,
1571 mbox->mapaddr);
1700 char *mbox;
1706 mbox = mlxsw_cmd_mbox_alloc();
1707 if (!mbox)
1720 err = mlxsw_cmd_query_fw(mlxsw_core, mbox);
1725 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox);
1727 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox);
1729 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox);
1731 if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) {
1736 if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) {
1743 mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox);
1745 if (mlxsw_cmd_mbox_query_fw_fr_rn_clk_bar_get(mbox) != 0) {
1752 mlxsw_cmd_mbox_query_fw_free_running_clock_offset_get(mbox);
1754 if (mlxsw_cmd_mbox_query_fw_utc_sec_bar_get(mbox) != 0) {
1761 mlxsw_cmd_mbox_query_fw_utc_sec_offset_get(mbox);
1763 if (mlxsw_cmd_mbox_query_fw_utc_nsec_bar_get(mbox) != 0) {
1770 mlxsw_cmd_mbox_query_fw_utc_nsec_offset_get(mbox);
1773 mlxsw_cmd_mbox_query_fw_lag_mode_support_get(mbox);
1775 mlxsw_cmd_mbox_query_fw_cff_support_get(mbox);
1777 num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox);
1778 err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages);
1782 err = mlxsw_pci_boardinfo(mlxsw_pci, mbox);
1786 err = mlxsw_core_resources_query(mlxsw_core, mbox, res);
1805 err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile, res);
1812 err = mlxsw_core_resources_query(mlxsw_core, mbox, res);
1820 err = mlxsw_pci_aqs_init(mlxsw_pci, mbox);
1856 mlxsw_cmd_mbox_free(mbox);
2031 * copy registers into mbox buffer.