Lines Matching refs:tid
76 atomic64_t tid;
375 MLXSW_ITEM64(emad, op_tlv, tid, 0x08, 0, 64);
476 u64 tid)
492 mlxsw_emad_op_tlv_tid_set(op_tlv, tid);
520 enum mlxsw_core_reg_access_type type, u64 tid)
541 mlxsw_emad_pack_op_tlv(buf, reg, type, tid);
683 u64 tid;
840 if (mlxsw_emad_get_tid(skb) == trans->tid) {
883 u64 tid;
898 get_random_bytes(&tid, 4);
899 tid <<= 32;
900 atomic64_set(&mlxsw_core->emad.tid, tid);
971 unsigned long cb_priv, u64 tid)
976 dev_dbg(mlxsw_core->bus_info->dev, "EMAD reg access (tid=%llx,reg_id=%x(%s),type=%s)\n",
977 tid, reg->id, mlxsw_reg_id_str(reg->id),
990 trans->tid = tid;
997 mlxsw_emad_construct(mlxsw_core, skb, reg, payload, type, trans->tid);
2673 return atomic64_inc_return(&mlxsw_core->emad.tid);
2684 u64 tid = mlxsw_core_tid_get(mlxsw_core);
2693 bulk_list, cb, cb_priv, tid);
2736 dev_warn(mlxsw_core->bus_info->dev, "EMAD retries (%d/%d) (tid=%llx)\n",
2737 trans->retries, MLXSW_EMAD_MAX_RETRY, trans->tid);
2739 dev_err(mlxsw_core->bus_info->dev, "EMAD reg access failed (tid=%llx,reg_id=%x(%s),type=%s,status=%x(%s))\n",
2740 trans->tid, trans->reg->id,
2747 "(tid=%llx,reg_id=%x(%s)) %s (%s)\n", trans->tid,