core/steering/dr_ste_v1.c

600 static void dr_ste_v1_arr_init_next_match(u8 **last_ste,
607 	*last_ste += DR_STE_SIZE;
608 	dr_ste_v1_init(*last_ste, MLX5DR_STE_LU_TYPE_DONT_CARE, 0, gvmi);
609 	dr_ste_v1_set_entry_type(*last_ste, DR_STE_V1_TYPE_MATCH);
611 	action = MLX5_ADDR_OF(ste_mask_and_match_v1, *last_ste, action);
615 static void dr_ste_v1_arr_init_next_match_range(u8 **last_ste,
619 	dr_ste_v1_arr_init_next_match(last_ste, added_stes, gvmi);
620 	dr_ste_v1_set_entry_type(*last_ste, DR_STE_V1_TYPE_MATCH_RANGES);
626 			      u8 *last_ste,
630 	u8 *action = MLX5_ADDR_OF(ste_match_bwc_v1, last_ste, action);
637 			dr_ste_v1_arr_init_next_match(&last_ste, added_stes,
640 					      last_ste, action);
643 		dr_ste_v1_set_pop_vlan(last_ste, action, attr->vlans.count);
654 			dr_ste_v1_arr_init_next_match(&last_ste, added_stes,
657 					      last_ste, action);
660 		dr_ste_v1_set_rewrite_actions(last_ste, action,
675 				dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
676 				action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
680 			dr_ste_v1_set_push_vlan(last_ste, action,
689 			dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
690 			action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
694 		dr_ste_v1_set_encap(last_ste, action,
703 			dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
704 			action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
709 		dr_ste_v1_set_encap_l3(last_ste,
717 			dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
718 			action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
721 		dr_ste_v1_set_insert_hdr(last_ste, action,
730 			dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
731 			action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
734 		dr_ste_v1_set_remove_hdr(last_ste, action,
744 			dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
745 			action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
759 		dr_ste_v1_arr_init_next_match_range(&last_ste, added_stes, attr->gvmi);
760 		dr_ste_v1_set_miss_addr(last_ste, attr->range.miss_icm_addr);
765 		dr_ste_v1_set_match_range_pkt_len(last_ste,
773 		dr_ste_v1_set_counter_id(last_ste, attr->ctr_id);
775 	dr_ste_v1_set_hit_gvmi(last_ste, attr->hit_gvmi);
776 	dr_ste_v1_set_hit_addr(last_ste, attr->final_icm_addr, 1);
782 			      u8 *last_ste,
786 	u8 *action = MLX5_ADDR_OF(ste_match_bwc_v1, last_ste, action);
792 		dr_ste_v1_set_rewrite_actions(last_ste, action,
802 		dr_ste_v1_set_rx_decap(last_ste, action);
811 			dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
812 			action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
825 			dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
826 			action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
830 		dr_ste_v1_set_pop_vlan(last_ste, action, attr->vlans.count);
843 			dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
844 			action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
849 		dr_ste_v1_set_rewrite_actions(last_ste, action,
864 				dr_ste_v1_arr_init_next_match(&last_ste,
868 						      last_ste, action);
871 			dr_ste_v1_set_push_vlan(last_ste, action,
883 			dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
884 			action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
888 		dr_ste_v1_set_counter_id(last_ste, attr->ctr_id);
894 			dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
895 			action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
898 		dr_ste_v1_set_encap(last_ste, action,
908 			dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
909 			action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
915 		dr_ste_v1_set_encap_l3(last_ste,
924 			dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
925 			action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
928 		dr_ste_v1_set_insert_hdr(last_ste, action,
938 			dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
939 			action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
944 		dr_ste_v1_set_remove_hdr(last_ste, action,
954 			dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
955 			action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
969 		dr_ste_v1_arr_init_next_match_range(&last_ste, added_stes, attr->gvmi);
970 		dr_ste_v1_set_miss_addr(last_ste, attr->range.miss_icm_addr);
975 		dr_ste_v1_set_match_range_pkt_len(last_ste,
981 	dr_ste_v1_set_hit_gvmi(last_ste, attr->hit_gvmi);
982 	dr_ste_v1_set_hit_addr(last_ste, attr->final_icm_addr, 1);