mlx5/core/port.c

149 	u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0};
151 	MLX5_SET(ptys_reg, in, local_port, local_port);
152 	MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
172 	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
180 	*link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);
181 	*proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
1111 	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
1121 	eproto->cap   = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
1123 	eproto->admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_admin);
1124 	eproto->oper  = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);