mlx5/core/port.c

7  * COPYING in the main directory of this source tree, or the
10  *     Redistribution and use in source and binary forms, with or
18  *      - Redistributions in binary form must reproduce the above
20  *        disclaimer in the documentation and/or other materials
45 	u32 *in = NULL;
48 	in = kvzalloc(inlen, GFP_KERNEL);
50 	if (!in || !out)
53 	data = MLX5_ADDR_OF(access_register_in, in, register_data);
56 	MLX5_SET(access_register_in, in, opcode, MLX5_CMD_OP_ACCESS_REG);
57 	MLX5_SET(access_register_in, in, op_mod, !write);
58 	MLX5_SET(access_register_in, in, argument, arg);
59 	MLX5_SET(access_register_in, in, register_id, reg_id);
61 	err = mlx5_cmd_do(dev, in, inlen, out, outlen);
63 		err = mlx5_cmd_check(dev, err, in, out);
72 	kvfree(in);
89 	u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {0};
92 	MLX5_SET(pcam_reg, in, feature_group, feature_group);
93 	MLX5_SET(pcam_reg, in, access_reg_group, access_reg_group);
95 	return mlx5_core_access_reg(dev, in, sz, pcam, sz, MLX5_REG_PCAM, 0, 0);
101 	u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {0};
104 	MLX5_SET(mcam_reg, in, feature_group, feature_group);
105 	MLX5_SET(mcam_reg, in, access_reg_group, access_reg_group);
107 	return mlx5_core_access_reg(dev, in, sz, mcam, sz, MLX5_REG_MCAM, 0, 0);
113 	u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {};
116 	MLX5_SET(qcam_reg, in, feature_group, feature_group);
117 	MLX5_SET(qcam_reg, in, access_reg_group, access_reg_group);
119 	return mlx5_core_access_reg(mdev, in, sz, qcam, sz, MLX5_REG_QCAM, 0, 0);
134 	struct mlx5_reg_pcap in;
137 	memset(&in, 0, sizeof(in));
138 	in.caps_127_96 = cpu_to_be32(caps);
139 	in.port_num = port_num;
141 	return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
149 	u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0};
151 	MLX5_SET(ptys_reg, in, local_port, local_port);
152 	MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
153 	return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
160 	u32 in[MLX5_ST_SZ_DW(mlcr_reg)]  = {0};
163 	MLX5_SET(mlcr_reg, in, local_port, 1);
164 	MLX5_SET(mlcr_reg, in, beacon_duration, beacon_duration);
165 	return mlx5_core_access_reg(dev, in, sizeof(in), out,
202 	u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
205 	MLX5_SET(paos_reg, in, local_port, 1);
206 	MLX5_SET(paos_reg, in, admin_status, status);
207 	MLX5_SET(paos_reg, in, ase, 1);
208 	return mlx5_core_access_reg(dev, in, sizeof(in), out,
216 	u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
220 	MLX5_SET(paos_reg, in, local_port, 1);
221 	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
233 	u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
236 	MLX5_SET(pmtu_reg, in, local_port, port);
237 	mlx5_core_access_reg(dev, in, sizeof(in), out,
250 	u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
253 	MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
254 	MLX5_SET(pmtu_reg, in, local_port, port);
255 	return mlx5_core_access_reg(dev, in, sizeof(in), out,
276 	u32 in[MLX5_ST_SZ_DW(pmlp_reg)] = {0};
280 	MLX5_SET(pmlp_reg, in, local_port, 1);
281 	err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
296 	u32 in[MLX5_ST_SZ_DW(mcia_reg)] = {};
301 	MLX5_SET(mcia_reg, in, i2c_device_address, MLX5_I2C_ADDR_LOW);
302 	MLX5_SET(mcia_reg, in, module, module_num);
303 	MLX5_SET(mcia_reg, in, device_address, 0);
304 	MLX5_SET(mcia_reg, in, page_number, 0);
305 	MLX5_SET(mcia_reg, in, size, 1);
306 	MLX5_SET(mcia_reg, in, l, 0);
308 	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
377 	u32 in[MLX5_ST_SZ_DW(mcia_reg)] = {};
385 	MLX5_SET(mcia_reg, in, l, 0);
386 	MLX5_SET(mcia_reg, in, size, size);
387 	MLX5_SET(mcia_reg, in, module, params->module_number);
388 	MLX5_SET(mcia_reg, in, device_address, params->offset);
389 	MLX5_SET(mcia_reg, in, page_number, params->page);
390 	MLX5_SET(mcia_reg, in, i2c_device_address, params->i2c_address);
392 	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
440 		/* Cross pages read, read until offset 256 in low page */
473 	u32 in[MLX5_ST_SZ_DW(pvlc_reg)] = {0};
475 	MLX5_SET(pvlc_reg, in, local_port, local_port);
476 	return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
499 	u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
501 	MLX5_SET(pfcc_reg, in, local_port, 1);
503 	return mlx5_core_access_reg(dev, in, sizeof(in), out,
509 	u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
512 	MLX5_SET(pfcc_reg, in, local_port, 1);
513 	MLX5_SET(pfcc_reg, in, pptx, tx_pause);
514 	MLX5_SET(pfcc_reg, in, pprx, rx_pause);
516 	return mlx5_core_access_reg(dev, in, sizeof(in), out,
545 	u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
548 	MLX5_SET(pfcc_reg, in, local_port, 1);
549 	MLX5_SET(pfcc_reg, in, pptx_mask_n, 1);
550 	MLX5_SET(pfcc_reg, in, pprx_mask_n, 1);
551 	MLX5_SET(pfcc_reg, in, ppan_mask_n, 1);
552 	MLX5_SET(pfcc_reg, in, critical_stall_mask, 1);
553 	MLX5_SET(pfcc_reg, in, minor_stall_mask, 1);
554 	MLX5_SET(pfcc_reg, in, device_stall_critical_watermark,
556 	MLX5_SET(pfcc_reg, in, device_stall_minor_watermark, stall_minor_watermark);
558 	return mlx5_core_access_reg(dev, in, sizeof(in), out,
586 	u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
589 	MLX5_SET(pfcc_reg, in, local_port, 1);
590 	MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
591 	MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
592 	MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
593 	MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);
595 	return mlx5_core_access_reg(dev, in, sizeof(in), out,
628 	u32 in[MLX5_ST_SZ_DW(dcbx_param)] = {0};
630 	MLX5_SET(dcbx_param, in, port_number, 1);
632 	return  mlx5_core_access_reg(mdev, in, sizeof(in), out,
633 				    sizeof(in), MLX5_REG_DCBX_PARAM, 0, 0);
636 int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in)
640 	MLX5_SET(dcbx_param, in, port_number, 1);
642 	return mlx5_core_access_reg(mdev, in, sizeof(out), out,
648 	u32 in[MLX5_ST_SZ_DW(qtct_reg)] = {0};
657 		MLX5_SET(qtct_reg, in, prio, i);
658 		MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);
660 		err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
673 	u32 in[MLX5_ST_SZ_DW(qtct_reg)];
677 	memset(in, 0, sizeof(in));
680 	MLX5_SET(qtct_reg, in, port_number, 1);
681 	MLX5_SET(qtct_reg, in, prio, prio);
683 	err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
692 static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in,
700 	return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
707 	u32 in[MLX5_ST_SZ_DW(qetc_reg)];
712 	memset(in, 0, sizeof(in));
713 	return mlx5_core_access_reg(mdev, in, sizeof(in), out, outlen,
719 	u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
723 		MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
724 		MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
727 	return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
754 	u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
758 		MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
759 		MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
762 	return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
791 	u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
795 	MLX5_SET(qetc_reg, in, port_number, 1);
798 		ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, in, tc_configuration[i]);
807 	return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
839 	u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)] = {};
841 	MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL);
842 	MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1);
843 	MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode);
844 	return mlx5_cmd_exec_in(mdev, set_wol_rol, in);
851 	u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)] = {};
854 	MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL);
855 	err = mlx5_cmd_exec_inout(mdev, query_wol_rol, in, out);
865 	u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
867 	MLX5_SET(pcmr_reg, in, local_port, 1);
868 	return mlx5_core_access_reg(mdev, in, sizeof(in), out,
872 int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen)
876 	return mlx5_core_access_reg(mdev, in, inlen, out,
882 	u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
885 	err = mlx5_query_ports_check(mdev, in, sizeof(in));
888 	MLX5_SET(pcmr_reg, in, local_port, 1);
889 	MLX5_SET(pcmr_reg, in, fcs_chk, enable);
890 	return mlx5_set_ports_check(mdev, in, sizeof(in));
913 	u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
915 	return mlx5_core_access_reg(mdev, in, sizeof(in), mtpps,
930 	u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
933 	MLX5_SET(mtppse_reg, in, pin, pin);
935 	err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
940 	*arm = MLX5_GET(mtppse_reg, in, event_arm);
941 	*mode = MLX5_GET(mtppse_reg, in, event_generation_mode);
949 	u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
951 	MLX5_SET(mtppse_reg, in, pin, pin);
952 	MLX5_SET(mtppse_reg, in, event_arm, arm);
953 	MLX5_SET(mtppse_reg, in, event_generation_mode, mode);
955 	return mlx5_core_access_reg(mdev, in, sizeof(in), out,
962 	u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
965 	MLX5_SET(qpts_reg, in, local_port, 1);
966 	MLX5_SET(qpts_reg, in, trust_state, trust_state);
968 	err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
976 	u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
979 	MLX5_SET(qpts_reg, in, local_port, 1);
981 	err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
994 	void *in;
997 	in = kzalloc(sz, GFP_KERNEL);
999 	if (!in || !out) {
1004 	MLX5_SET(qpdpm_reg, in, local_port, 1);
1005 	err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
1009 	memcpy(in, out, sz);
1010 	MLX5_SET(qpdpm_reg, in, local_port, 1);
1013 	qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, in, dscp[dscp]);
1016 	err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 1);
1019 	kfree(in);
1031 	void *in;
1035 	in = kzalloc(sz, GFP_KERNEL);
1037 	if (!in || !out) {
1042 	MLX5_SET(qpdpm_reg, in, local_port, 1);
1043 	err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
1053 	kfree(in);
1058 /* speed in units of 1Mb */
1212 	u32 in[MLX5_ST_SZ_DW(mpir_reg)] = {};
1215 	MLX5_SET(mpir_reg, in, local_port, 1);
1217 	return mlx5_core_access_reg(dev, in, sz, mpir, sz, MLX5_REG_MPIR, 0, 0);