Lines Matching defs:set_hca_cap

423 	return mlx5_cmd_exec_in(dev, set_hca_cap, in);
428 void *set_hca_cap;
446 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
449 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
457 void *set_hca_cap;
469 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
470 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur,
478 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
538 void *set_hca_cap;
552 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
554 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur,
556 MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1);
564 void *set_hca_cap;
572 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
574 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur,
581 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
594 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
598 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
604 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
606 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
610 set_hca_cap,
615 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
618 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
620 MLX5_SET(cmd_hca_cap, set_hca_cap,
625 set_hca_cap,
630 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
633 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
635 mlx5_vhca_state_cap_handle(dev, set_hca_cap);
638 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
642 MLX5_SET(cmd_hca_cap, set_hca_cap, roce,
647 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list,
675 void *set_hca_cap;
689 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
690 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur,
692 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
695 MLX5_SET(roce_cap, set_hca_cap, qp_ooo_transmit_default, 1);
704 void *set_hca_cap;
718 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
719 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur,
721 MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1);
728 static int set_hca_cap(struct mlx5_core_dev *dev)
1239 err = set_hca_cap(dev);
1241 mlx5_core_err(dev, "set_hca_cap failed\n");