Lines Matching defs:in
87 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
89 MLX5_SET(mfrl_reg, in, reset_level, reset_level);
90 MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
91 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_resp, sync_resp);
92 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, sync_start);
94 return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 1);
101 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
104 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 0);
137 NL_SET_ERR_MSG_MOD(extack, "Sync reset still in progress");
160 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
165 MLX5_SET(mfrl_reg, in, reset_level, MLX5_MFRL_REG_RESET_LEVEL3);
166 MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
167 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, 1);
168 err = mlx5_access_reg(dev, in, sizeof(in), out, sizeof(out),
180 return mlx5_cmd_check(dev, err, in, out);