core/fpga/conn.c

110 	if (unlikely(conn->qp.rq.pc - conn->qp.rq.cc >= conn->qp.rq.size)) {
115 	ix = conn->qp.rq.pc & (conn->qp.rq.size - 1);
116 	data = mlx5_wq_cyc_get_wqe(&conn->qp.wq.rq, ix);
121 	conn->qp.rq.pc++;
122 	conn->qp.rq.bufs[ix] = buf;
126 	*conn->qp.wq.rq.db = cpu_to_be32(conn->qp.rq.pc & 0xffff);
135 	*conn->qp.wq.sq.db = cpu_to_be32(conn->qp.sq.pc);
149 	ix = conn->qp.sq.pc & (conn->qp.sq.size - 1);
151 	ctrl = mlx5_wq_cyc_get_wqe(&conn->qp.wq.sq, ix);
166 	ctrl->opmod_idx_opcode = cpu_to_be32(((conn->qp.sq.pc & 0xffff) << 8) |
168 	ctrl->qpn_ds = cpu_to_be32(size | (conn->qp.qpn << 8));
170 	conn->qp.sq.pc++;
171 	conn->qp.sq.bufs[ix] = buf;
181 	if (!conn->qp.active)
189 	spin_lock_irqsave(&conn->qp.sq.lock, flags);
191 	if (conn->qp.sq.pc - conn->qp.sq.cc >= conn->qp.sq.size) {
192 		list_add_tail(&buf->list, &conn->qp.sq.backlog);
199 	spin_unlock_irqrestore(&conn->qp.sq.lock, flags);
256 	ix = be16_to_cpu(cqe->wqe_counter) & (conn->qp.rq.size - 1);
257 	buf = conn->qp.rq.bufs[ix];
258 	conn->qp.rq.bufs[ix] = NULL;
259 	conn->qp.rq.cc++;
270 	if (unlikely(status || !conn->qp.active)) {
271 		conn->qp.active = false;
297 	spin_lock_irqsave(&conn->qp.sq.lock, flags);
299 	ix = be16_to_cpu(cqe->wqe_counter) & (conn->qp.sq.size - 1);
300 	buf = conn->qp.sq.bufs[ix];
301 	conn->qp.sq.bufs[ix] = NULL;
302 	conn->qp.sq.cc++;
305 	if (unlikely(!list_empty(&conn->qp.sq.backlog))) {
306 		if (likely(conn->qp.active)) {
307 			nextbuf = list_first_entry(&conn->qp.sq.backlog,
314 	spin_unlock_irqrestore(&conn->qp.sq.lock, flags);
329 		conn->qp.active = false;
395 	if (unlikely(!conn->qp.active))
406 	if (unlikely(!conn->qp.active))
508 	return mlx5_wq_qp_create(mdev, &wqp, qpc, &conn->qp.wq,
509 				 &conn->qp.wq_ctrl);
522 	conn->qp.rq.pc = 0;
523 	conn->qp.rq.cc = 0;
524 	conn->qp.rq.size = roundup_pow_of_two(rx_size);
525 	conn->qp.sq.pc = 0;
526 	conn->qp.sq.cc = 0;
527 	conn->qp.sq.size = roundup_pow_of_two(tx_size);
530 	MLX5_SET(qpc, temp_qpc, log_rq_size, ilog2(conn->qp.rq.size));
531 	MLX5_SET(qpc, temp_qpc, log_sq_size, ilog2(conn->qp.sq.size));
536 	conn->qp.rq.bufs = kvcalloc(conn->qp.rq.size,
537 				    sizeof(conn->qp.rq.bufs[0]),
539 	if (!conn->qp.rq.bufs) {
544 	conn->qp.sq.bufs = kvcalloc(conn->qp.sq.size,
545 				    sizeof(conn->qp.sq.bufs[0]),
547 	if (!conn->qp.sq.bufs) {
554 		conn->qp.wq_ctrl.buf.npages;
564 		 conn->qp.wq_ctrl.buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
571 	MLX5_SET(qpc, qpc, log_rq_size, ilog2(conn->qp.rq.size));
573 	MLX5_SET(qpc, qpc, log_sq_size, ilog2(conn->qp.sq.size));
577 	MLX5_SET64(qpc, qpc, dbr_addr, conn->qp.wq_ctrl.db.dma);
581 	mlx5_fill_page_frag_array(&conn->qp.wq_ctrl.buf,
589 	conn->qp.qpn = MLX5_GET(create_qp_out, out, qpn);
590 	mlx5_fpga_dbg(fdev, "Created QP #0x%x\n", conn->qp.qpn);
595 	kvfree(conn->qp.sq.bufs);
597 	kvfree(conn->qp.rq.bufs);
599 	mlx5_wq_destroy(&conn->qp.wq_ctrl);
609 	for (ix = 0; ix < conn->qp.rq.size; ix++) {
610 		if (!conn->qp.rq.bufs[ix])
612 		mlx5_fpga_conn_unmap_buf(conn, conn->qp.rq.bufs[ix]);
613 		kfree(conn->qp.rq.bufs[ix]);
614 		conn->qp.rq.bufs[ix] = NULL;
623 	for (ix = 0; ix < conn->qp.sq.size; ix++) {
624 		buf = conn->qp.sq.bufs[ix];
627 		conn->qp.sq.bufs[ix] = NULL;
633 	list_for_each_entry_safe(buf, temp, &conn->qp.sq.backlog, list) {
647 	MLX5_SET(destroy_qp_in, in, qpn, conn->qp.qpn);
652 	kvfree(conn->qp.sq.bufs);
653 	kvfree(conn->qp.rq.bufs);
654 	mlx5_wq_destroy(&conn->qp.wq_ctrl);
662 	mlx5_fpga_dbg(conn->fdev, "Modifying QP %u to RST\n", conn->qp.qpn);
665 	MLX5_SET(qp_2rst_in, in, qpn, conn->qp.qpn);
677 	mlx5_fpga_dbg(conn->fdev, "Modifying QP %u to INIT\n", conn->qp.qpn);
688 	MLX5_SET64(qpc, qpc, dbr_addr, conn->qp.wq_ctrl.db.dma);
691 	MLX5_SET(rst2init_qp_in, in, qpn, conn->qp.qpn);
719 		 conn->qp.sgid_index);
726 	MLX5_SET(init2rtr_qp_in, in, qpn, conn->qp.qpn);
751 	MLX5_SET(rtr2rts_qp_in, in, qpn, conn->qp.qpn);
781 	conn->qp.active = true;
826 	INIT_LIST_HEAD(&conn->qp.sq.backlog);
828 	spin_lock_init(&conn->qp.sq.lock);
847 	err = mlx5_core_reserved_gid_alloc(fdev->mdev, &conn->qp.sgid_index);
854 	err = mlx5_core_roce_gid_set(fdev->mdev, conn->qp.sgid_index,
864 	mlx5_fpga_dbg(fdev, "Reserved SGID index %u\n", conn->qp.sgid_index);
894 	MLX5_SET(fpga_qpc, conn->fpga_qpc, remote_qpn, conn->qp.qpn);
923 	mlx5_core_roce_gid_set(fdev->mdev, conn->qp.sgid_index, 0, 0, NULL,
926 	mlx5_core_reserved_gid_free(fdev->mdev, conn->qp.sgid_index);
935 	conn->qp.active = false;
943 	mlx5_core_roce_gid_set(conn->fdev->mdev, conn->qp.sgid_index, 0, 0,
945 	mlx5_core_reserved_gid_free(conn->fdev->mdev, conn->qp.sgid_index);