core/fpga/conn.c

57 	dma_device = mlx5_core_dma_dev(conn->fdev->mdev);
89 	dma_device = mlx5_core_dma_dev(conn->fdev->mdev);
223 static int mlx5_fpga_conn_create_mkey(struct mlx5_core_dev *mdev, u32 pdn,
244 	err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
414 	struct mlx5_core_dev *mdev = fdev->mdev;
427 	wqp.buf_numa_node = mdev->priv.numa_node;
428 	wqp.db_numa_node  = mdev->priv.numa_node;
430 	err = mlx5_cqwq_create(mdev, &wqp, temp_cqc, &conn->cq.wq,
448 	err = mlx5_comp_eqn_get(mdev, smp_processor_id(), &eqn);
465 	err = mlx5_core_create_cq(mdev, &conn->cq.mcq, in, inlen, out, sizeof(out));
495 	mlx5_core_destroy_cq(conn->fdev->mdev, &conn->cq.mcq);
502 	struct mlx5_core_dev *mdev = fdev->mdev;
505 	wqp.buf_numa_node = mdev->priv.numa_node;
506 	wqp.db_numa_node  = mdev->priv.numa_node;
508 	return mlx5_wq_qp_create(mdev, &wqp, qpc, &conn->qp.wq,
517 	struct mlx5_core_dev *mdev = fdev->mdev;
576 	MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(mdev));
578 	if (MLX5_CAP_GEN(mdev, cqe_version) == 1)
585 	err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
643 	struct mlx5_core_dev *dev = conn->fdev->mdev;
659 	struct mlx5_core_dev *mdev = conn->fdev->mdev;
667 	return mlx5_cmd_exec_in(mdev, qp_2rst, in);
674 	struct mlx5_core_dev *mdev = fdev->mdev;
693 	return mlx5_cmd_exec_in(mdev, rst2init_qp, in);
700 	struct mlx5_core_dev *mdev = fdev->mdev;
708 	MLX5_SET(qpc, qpc, log_msg_max, (u8)MLX5_CAP_GEN(mdev, log_max_msg));
717 		 MLX5_CAP_ROCE(mdev, r_roce_min_src_udp_port));
728 	return mlx5_cmd_exec_in(mdev, init2rtr_qp, in);
735 	struct mlx5_core_dev *mdev = fdev->mdev;
754 	return mlx5_cmd_exec_in(mdev, rtr2rts_qp, in);
763 	err = mlx5_fpga_modify_qp(conn->fdev->mdev, conn->fpga_qpn,
803 	if (mlx5_fpga_modify_qp(conn->fdev->mdev, conn->fpga_qpn,
834 	err = mlx5_query_mac_address(fdev->mdev, remote_mac);
847 	err = mlx5_core_reserved_gid_alloc(fdev->mdev, &conn->qp.sgid_index);
854 	err = mlx5_core_roce_gid_set(fdev->mdev, conn->qp.sgid_index,
898 	err = mlx5_fpga_create_qp(fdev->mdev, &conn->fpga_qpc,
917 	mlx5_fpga_destroy_qp(conn->fdev->mdev, conn->fpga_qpn);
923 	mlx5_core_roce_gid_set(fdev->mdev, conn->qp.sgid_index, 0, 0, NULL,
926 	mlx5_core_reserved_gid_free(fdev->mdev, conn->qp.sgid_index);
939 	mlx5_fpga_destroy_qp(conn->fdev->mdev, conn->fpga_qpn);
943 	mlx5_core_roce_gid_set(conn->fdev->mdev, conn->qp.sgid_index, 0, 0,
945 	mlx5_core_reserved_gid_free(conn->fdev->mdev, conn->qp.sgid_index);
953 	err = mlx5_nic_vport_enable_roce(fdev->mdev);
959 	fdev->conn_res.uar = mlx5_get_uars_page(fdev->mdev);
968 	err = mlx5_core_alloc_pd(fdev->mdev, &fdev->conn_res.pdn);
975 	err = mlx5_fpga_conn_create_mkey(fdev->mdev, fdev->conn_res.pdn,
986 	mlx5_core_dealloc_pd(fdev->mdev, fdev->conn_res.pdn);
988 	mlx5_put_uars_page(fdev->mdev, fdev->conn_res.uar);
990 	mlx5_nic_vport_disable_roce(fdev->mdev);
997 	mlx5_core_destroy_mkey(fdev->mdev, fdev->conn_res.mkey);
998 	mlx5_core_dealloc_pd(fdev->mdev, fdev->conn_res.pdn);
999 	mlx5_put_uars_page(fdev->mdev, fdev->conn_res.uar);
1000 	mlx5_nic_vport_disable_roce(fdev->mdev);