core/fpga/cmd.c

7  * COPYING in the main directory of this source tree, or the
10  *     Redistribution and use in source and binary forms, with or
18  *      - Redistributions in binary form must reproduce the above
20  *        disclaimer in the documentation and/or other materials
46 	u32 in[MLX5_FPGA_ACCESS_REG_SZ] = {0};
57 	MLX5_SET(fpga_access_reg, in, size, size);
58 	MLX5_SET64(fpga_access_reg, in, address, addr);
60 		memcpy(MLX5_ADDR_OF(fpga_access_reg, in, data), buf, size);
62 	err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
75 	u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0};
77 	return mlx5_core_access_reg(dev, in, sizeof(in), dev->caps.fpga,
84 	u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
87 	MLX5_SET(fpga_ctrl, in, operation, op);
89 	return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
127 	u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
131 	err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
146 	u32 in[MLX5_ST_SZ_DW(fpga_create_qp_in)] = {};
149 	MLX5_SET(fpga_create_qp_in, in, opcode, MLX5_CMD_OP_FPGA_CREATE_QP);
150 	memcpy(MLX5_ADDR_OF(fpga_create_qp_in, in, fpga_qpc), fpga_qpc,
153 	ret = mlx5_cmd_exec_inout(dev, fpga_create_qp, in, out);
167 	u32 in[MLX5_ST_SZ_DW(fpga_modify_qp_in)] = {};
169 	MLX5_SET(fpga_modify_qp_in, in, opcode, MLX5_CMD_OP_FPGA_MODIFY_QP);
170 	MLX5_SET(fpga_modify_qp_in, in, field_select, fields);
171 	MLX5_SET(fpga_modify_qp_in, in, fpga_qpn, fpga_qpn);
172 	memcpy(MLX5_ADDR_OF(fpga_modify_qp_in, in, fpga_qpc), fpga_qpc,
175 	return mlx5_cmd_exec_in(dev, fpga_modify_qp, in);
182 	u32 in[MLX5_ST_SZ_DW(fpga_query_qp_in)] = {};
185 	MLX5_SET(fpga_query_qp_in, in, opcode, MLX5_CMD_OP_FPGA_QUERY_QP);
186 	MLX5_SET(fpga_query_qp_in, in, fpga_qpn, fpga_qpn);
188 	ret = mlx5_cmd_exec_inout(dev, fpga_query_qp, in, out);
199 	u32 in[MLX5_ST_SZ_DW(fpga_destroy_qp_in)] = {};
201 	MLX5_SET(fpga_destroy_qp_in, in, opcode, MLX5_CMD_OP_FPGA_DESTROY_QP);
202 	MLX5_SET(fpga_destroy_qp_in, in, fpga_qpn, fpga_qpn);
204 	return mlx5_cmd_exec_in(dev, fpga_destroy_qp, in);
211 	u32 in[MLX5_ST_SZ_DW(fpga_query_qp_counters_in)] = {};
214 	MLX5_SET(fpga_query_qp_counters_in, in, opcode,
216 	MLX5_SET(fpga_query_qp_counters_in, in, clear, clear);
217 	MLX5_SET(fpga_query_qp_counters_in, in, fpga_qpn, fpga_qpn);
219 	ret = mlx5_cmd_exec_inout(dev, fpga_query_qp_counters, in, out);