Lines Matching refs:max_rate

19 	u32 max_rate;
26 u32 tsar_ix, u32 max_rate, u32 bw_share)
33 MLX5_SET(scheduling_context, sched_ctx, max_average_bw, max_rate);
46 u32 max_rate, u32 bw_share, struct netlink_ext_ack *extack)
54 max_rate, bw_share);
58 trace_mlx5_esw_group_qos_config(dev, group, group->tsar_ix, bw_share, max_rate);
65 u32 max_rate, u32 bw_share,
76 max_rate, bw_share);
85 trace_mlx5_esw_vport_qos_config(vport, bw_share, max_rate);
154 err = esw_qos_vport_config(esw, evport, evport->qos.max_rate, bw_share, extack);
178 err = esw_qos_group_config(esw, group, group->max_rate, bw_share, extack);
222 u32 max_rate, struct netlink_ext_ack *extack)
224 u32 act_max_rate = max_rate;
231 if (max_rate && !max_rate_supported)
233 if (max_rate == evport->qos.max_rate)
239 if (evport->qos.group && !max_rate)
240 act_max_rate = evport->qos.group->max_rate;
245 evport->qos.max_rate = max_rate;
283 u32 max_rate, struct netlink_ext_ack *extack)
289 if (group->max_rate == max_rate)
292 err = esw_qos_group_config(esw, group, max_rate, group->bw_share, extack);
296 group->max_rate = max_rate;
303 vport->qos.group != group || vport->qos.max_rate)
306 err = esw_qos_vport_config(esw, vport, max_rate, vport->qos.bw_share, extack);
317 u32 max_rate, u32 bw_share)
332 MLX5_SET(scheduling_context, sched_ctx, max_average_bw, max_rate);
354 u32 max_rate;
366 max_rate = vport->qos.max_rate ? vport->qos.max_rate : new_group->max_rate;
372 err = esw_qos_vport_create_sched_element(esw, vport, max_rate, vport->qos.bw_share);
382 max_rate = vport->qos.max_rate ? vport->qos.max_rate : curr_group->max_rate;
383 if (esw_qos_vport_create_sched_element(esw, vport, max_rate, vport->qos.bw_share))
636 u32 max_rate, u32 bw_share, struct netlink_ext_ack *extack)
650 err = esw_qos_vport_create_sched_element(esw, vport, max_rate, bw_share);
655 trace_mlx5_esw_vport_qos_create(vport, bw_share, max_rate);
689 u32 max_rate, u32 min_rate)
700 err = esw_qos_set_vport_max_rate(esw, vport, max_rate, NULL);