mlx5/core/en_stats.c

622 	u32 out[MLX5_ST_SZ_DW(query_q_counter_out)] = {};
634 			ret = mlx5_cmd_exec_inout(pos, query_q_counter, in, out);
637 							     out, out_of_buffer);
645 		ret = mlx5_cmd_exec_inout(priv->mdev, query_q_counter, in, out);
648 							    out, out_of_buffer);
724 	u32 *out = (u32 *)priv->stats.vnic.query_vnic_env_out;
732 	mlx5_cmd_exec_inout(mdev, query_vnic_env, in, out);
827 	u32 *out = (u32 *)priv->stats.vport.query_vport_out;
832 	mlx5_cmd_exec_inout(mdev, query_vport_counter, in, out);
894 	void *out;
900 	out = pstats->IEEE_802_3_counters;
902 	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1052 	void *out;
1055 	out = pstats->RFC_2863_counters;
1057 	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1111 	void *out;
1117 	out = pstats->RFC_2819_counters;
1119 	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1190 			goto out;
1220 out:
1318 	void *out;
1321 	out = pstats->phy_counters;
1323 	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1328 	out = pstats->phy_statistical_counters;
1330 	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1337 	u32 out[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1343 	mlx5_core_access_reg(priv->mdev, in, sz, out,
1346 	stats->link_down_events = MLX5_GET(ppcnt_reg, out,
1352 	u32 out[MLX5_ST_SZ_DW(pmlp_reg)] = {};
1357 	err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
1362 	return MLX5_GET(pmlp_reg, out, width);
1413 	u32 out[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1423 	if (mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0))
1430 		fec_set_rs_stats(fec_stats, out);
1433 		fec_set_fc_stats(fec_stats, out, fec_num_lanes(mdev));
1512 	void *out;
1518 	out = pstats->eth_ext_counters;
1520 	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1616 	void *out;
1621 	out = pcie_stats->pcie_perf_counters;
1623 	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
1711 	void *out;
1720 		out = pstats->per_tc_prio_counters[prio];
1722 		mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1742 	void *out;
1751 		out = pstats->per_tc_congest_prio_counters[prio];
1753 		mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1963 	void *out;
1971 		out = pstats->per_prio_counters[prio];
1973 		mlx5_core_access_reg(mdev, in, sz, out, sz,