mlx5/core/en_stats.c

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481 	/* Pairs with smp_store_release in mlx5e_open_qos_sq. */
623 	u32 in[MLX5_ST_SZ_DW(query_q_counter_in)] = {};
628 	MLX5_SET(query_q_counter_in, in, opcode, MLX5_CMD_OP_QUERY_Q_COUNTER);
632 			MLX5_SET(query_q_counter_in, in, counter_set_id,
634 			ret = mlx5_cmd_exec_inout(pos, query_q_counter, in, out);
643 		MLX5_SET(query_q_counter_in, in, counter_set_id,
645 		ret = mlx5_cmd_exec_inout(priv->mdev, query_q_counter, in, out);
725 	u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
731 	MLX5_SET(query_vnic_env_in, in, opcode, MLX5_CMD_OP_QUERY_VNIC_ENV);
732 	mlx5_cmd_exec_inout(mdev, query_vnic_env, in, out);
828 	u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {};
831 	MLX5_SET(query_vport_counter_in, in, opcode, MLX5_CMD_OP_QUERY_VPORT_COUNTER);
832 	mlx5_cmd_exec_inout(mdev, query_vport_counter, in, out);
892 	u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
899 	MLX5_SET(ppcnt_reg, in, local_port, 1);
901 	MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
902 	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
913 	u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
919 	MLX5_SET(ppcnt_reg, in, local_port, 1);
920 	MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
921 	return mlx5_core_access_reg(mdev, in, sz, ppcnt_ieee_802_3,
1050 	u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1054 	MLX5_SET(ppcnt_reg, in, local_port, 1);
1056 	MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
1057 	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1109 	u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1116 	MLX5_SET(ppcnt_reg, in, local_port, 1);
1118 	MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
1119 	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1142 	u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1145 	MLX5_SET(ppcnt_reg, in, local_port, 1);
1146 	MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
1147 	if (mlx5_core_access_reg(mdev, in, sz, ppcnt_RFC_2819_counters,
1282 	/* link_down_events_phy has special handling since it is not stored in __be64 format */
1312 	u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1316 	MLX5_SET(ppcnt_reg, in, local_port, 1);
1318 	MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
1319 	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1325 	MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
1326 	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1334 	u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1337 	MLX5_SET(ppcnt_reg, in, local_port, 1);
1338 	MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
1339 	mlx5_core_access_reg(priv->mdev, in, sz, out,
1349 	u32 in[MLX5_ST_SZ_DW(pmlp_reg)] = {};
1352 	MLX5_SET(pmlp_reg, in, local_port, 1);
1353 	err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
1410 	u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1417 	MLX5_SET(ppcnt_reg, in, local_port, 1);
1418 	MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
1419 	if (mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0))
1438 	u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1441 	MLX5_SET(ppcnt_reg, in, local_port, 1);
1442 	MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
1443 	if (mlx5_core_access_reg(mdev, in, sz, ppcnt_phy_statistical,
1506 	u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1513 	MLX5_SET(ppcnt_reg, in, local_port, 1);
1515 	MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
1516 	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1610 	u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
1618 	MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
1619 	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
1705 	u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1713 	MLX5_SET(ppcnt_reg, in, pnat, 2);
1714 	MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP);
1717 		MLX5_SET(ppcnt_reg, in, prio_tc, prio);
1718 		mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1736 	u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1744 	MLX5_SET(ppcnt_reg, in, pnat, 2);
1745 	MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP);
1748 		MLX5_SET(ppcnt_reg, in, prio_tc, prio);
1749 		mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1956 	u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1964 	MLX5_SET(ppcnt_reg, in, local_port, 1);
1965 	MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
1968 		MLX5_SET(ppcnt_reg, in, prio_tc, prio);
1969 		mlx5_core_access_reg(mdev, in, sz, out, sz,
2306 	/* Pairs with smp_store_release in mlx5e_open_qos_sq. */
2312 	/* Pairs with smp_store_release in mlx5e_open_qos_sq. */
2327 	/* Pairs with smp_store_release in mlx5e_open_qos_sq. */