core/en_accel/ktls_tx.c

525 static void tx_fill_wi(struct mlx5e_txqsq *sq,
529 	struct mlx5e_tx_wqe_info *wi = &sq->db.wqe_info[pi];
549 post_static_params(struct mlx5e_txqsq *sq,
557 	pi = mlx5e_txqsq_get_next_pi(sq, num_wqebbs);
558 	wqe = MLX5E_TLS_FETCH_SET_STATIC_PARAMS_WQE(sq, pi);
559 	mlx5e_ktls_build_static_params(wqe, sq->pc, sq->sqn, &priv_tx->crypto_info,
563 	tx_fill_wi(sq, pi, num_wqebbs, 0, NULL);
564 	sq->pc += num_wqebbs;
568 post_progress_params(struct mlx5e_txqsq *sq,
576 	pi = mlx5e_txqsq_get_next_pi(sq, num_wqebbs);
577 	wqe = MLX5E_TLS_FETCH_SET_PROGRESS_PARAMS_WQE(sq, pi);
578 	mlx5e_ktls_build_progress_params(wqe, sq->pc, sq->sqn, priv_tx->tisn, fence, 0,
580 	tx_fill_wi(sq, pi, num_wqebbs, 0, NULL);
581 	sq->pc += num_wqebbs;
584 static void tx_post_fence_nop(struct mlx5e_txqsq *sq)
586 	struct mlx5_wq_cyc *wq = &sq->wq;
587 	u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
589 	tx_fill_wi(sq, pi, 1, 0, NULL);
591 	mlx5e_post_nop_fence(wq, sq->sqn, &sq->pc);
595 mlx5e_ktls_tx_post_param_wqes(struct mlx5e_txqsq *sq,
602 		post_static_params(sq, priv_tx, fence_first_post);
604 	post_progress_params(sq, priv_tx, progress_fence);
605 	tx_post_fence_nop(sq);
677 tx_post_resync_params(struct mlx5e_txqsq *sq,
711 	mlx5e_ktls_tx_post_param_wqes(sq, priv_tx, skip_static_post, true);
715 tx_post_resync_dump(struct mlx5e_txqsq *sq, skb_frag_t *frag, u32 tisn)
726 	pi = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->pc);
727 	wqe = MLX5E_TLS_FETCH_DUMP_WQE(sq, pi);
734 	cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8)  | MLX5_OPCODE_DUMP);
735 	cseg->qpn_ds           = cpu_to_be32((sq->sqn << 8) | ds_cnt);
739 	dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
741 	if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
745 	dseg->lkey       = sq->mkey_be;
747 	mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE);
749 	tx_fill_wi(sq, pi, MLX5E_KTLS_DUMP_WQEBBS, fsz, skb_frag_page(frag));
750 	sq->pc += MLX5E_KTLS_DUMP_WQEBBS;
755 void mlx5e_ktls_tx_handle_resync_dump_comp(struct mlx5e_txqsq *sq,
762 	dma = mlx5e_dma_get(sq, (*dma_fifo_cc)++);
763 	stats = sq->stats;
765 	mlx5e_tx_dma_unmap(sq->pdev, dma);
773 			 struct mlx5e_txqsq *sq,
789 	tx_post_resync_params(sq, priv_tx, info.rcd_sn);
801 			fsz = min_t(unsigned int, sq->hw_mtu, orig_fsz - frag_offset);
803 			if (tx_post_resync_dump(sq, f, priv_tx->tisn)) {
829 bool mlx5e_ktls_handle_tx_skb(struct net_device *netdev, struct mlx5e_txqsq *sq,
834 	struct mlx5e_sq_stats *stats = sq->stats;
844 	mlx5e_tx_mpwqe_ensure_complete(sq);
858 		mlx5e_ktls_tx_post_param_wqes(sq, priv_tx, false, false);
863 			mlx5e_ktls_tx_handle_ooo(priv_tx, sq, datalen, seq);