Lines Matching defs:priv_rx

28 	struct mlx5e_ktls_offload_context_rx *priv_rx;
63 static bool mlx5e_ktls_priv_rx_put(struct mlx5e_ktls_offload_context_rx *priv_rx)
65 if (!refcount_dec_and_test(&priv_rx->resync.refcnt))
68 kfree(priv_rx);
72 static void mlx5e_ktls_priv_rx_get(struct mlx5e_ktls_offload_context_rx *priv_rx)
74 refcount_inc(&priv_rx->resync.refcnt);
105 struct mlx5e_ktls_offload_context_rx *priv_rx;
110 priv_rx = container_of(accel_rule, struct mlx5e_ktls_offload_context_rx, rule);
111 if (unlikely(test_bit(MLX5E_PRIV_RX_FLAG_DELETING, priv_rx->flags)))
114 rule = mlx5e_accel_fs_add_sk(accel_rule->priv->fs, priv_rx->sk,
115 mlx5e_tir_get_tirn(&priv_rx->tir),
120 complete(&priv_rx->add_ctx);
137 struct mlx5e_ktls_offload_context_rx *priv_rx)
149 mlx5e_ktls_build_static_params(wqe, sq->pc, sq->sqn, &priv_rx->crypto_info,
150 mlx5e_tir_get_tirn(&priv_rx->tir),
151 mlx5_crypto_dek_get_id(priv_rx->dek),
152 priv_rx->resync.seq, false,
157 .tls_set_params.priv_rx = priv_rx,
167 struct mlx5e_ktls_offload_context_rx *priv_rx,
181 mlx5e_tir_get_tirn(&priv_rx->tir),
187 .tls_set_params.priv_rx = priv_rx,
197 struct mlx5e_ktls_offload_context_rx *priv_rx,
208 cseg = post_static_params(sq, priv_rx);
211 cseg = post_progress_params(sq, priv_rx, next_record_tcp_sn);
222 priv_rx->rq_stats->tls_resync_req_skip++;
224 complete(&priv_rx->add_ctx);
230 struct mlx5e_ktls_offload_context_rx *priv_rx)
235 BUILD_BUG_ON(sizeof(priv_rx) > TLS_DRIVER_STATE_SIZE_RX);
237 *ctx = priv_rx;
253 struct mlx5e_ktls_offload_context_rx *priv_rx)
278 buf->priv_rx = priv_rx;
303 psv->psv_index[0] = cpu_to_be32(mlx5e_tir_get_tirn(&priv_rx->tir));
323 priv_rx->rq_stats->tls_resync_req_skip++;
332 struct mlx5e_ktls_offload_context_rx *priv_rx;
338 priv_rx = container_of(resync, struct mlx5e_ktls_offload_context_rx, resync);
340 if (unlikely(test_bit(MLX5E_PRIV_RX_FLAG_DELETING, priv_rx->flags))) {
341 mlx5e_ktls_priv_rx_put(priv_rx);
345 c = resync->priv->channels.c[priv_rx->rxq];
348 if (resync_post_get_progress_params(sq, priv_rx))
349 mlx5e_ktls_priv_rx_put(priv_rx);
363 static void resync_handle_seq_match(struct mlx5e_ktls_offload_context_rx *priv_rx,
375 spin_lock_bh(&priv_rx->lock);
376 switch (priv_rx->crypto_info.crypto_info.cipher_type) {
379 &priv_rx->crypto_info.crypto_info_128;
381 memcpy(info->rec_seq, &priv_rx->resync.sw_rcd_sn_be,
387 &priv_rx->crypto_info.crypto_info_256;
389 memcpy(info->rec_seq, &priv_rx->resync.sw_rcd_sn_be,
395 priv_rx->crypto_info.crypto_info.cipher_type);
396 spin_unlock_bh(&priv_rx->lock);
401 if (list_empty(&priv_rx->list)) {
402 list_add_tail(&priv_rx->list, &ktls_resync->list);
405 spin_unlock_bh(&priv_rx->lock);
427 struct mlx5e_ktls_offload_context_rx *priv_rx;
432 priv_rx = buf->priv_rx;
434 if (unlikely(test_bit(MLX5E_PRIV_RX_FLAG_DELETING, priv_rx->flags)))
445 priv_rx->rq_stats->tls_resync_req_skip++;
450 tls_offload_rx_resync_async_request_end(priv_rx->sk, cpu_to_be32(hw_seq));
451 priv_rx->rq_stats->tls_resync_req_end++;
453 mlx5e_ktls_priv_rx_put(priv_rx);
463 struct mlx5e_ktls_offload_context_rx *priv_rx;
466 priv_rx = mlx5e_get_ktls_rx_priv_ctx(tls_get_ctx(sk));
467 if (unlikely(!priv_rx))
470 if (unlikely(test_bit(MLX5E_PRIV_RX_FLAG_DELETING, priv_rx->flags)))
473 resync = &priv_rx->resync;
474 mlx5e_ktls_priv_rx_get(priv_rx);
476 mlx5e_ktls_priv_rx_put(priv_rx);
541 struct mlx5e_ktls_offload_context_rx *priv_rx;
546 priv_rx = mlx5e_get_ktls_rx_priv_ctx(tls_get_ctx(sk));
547 if (unlikely(!priv_rx))
550 resync = &priv_rx->resync;
555 c = priv->channels.c[priv_rx->rxq];
557 resync_handle_seq_match(priv_rx, c);
585 struct mlx5e_ktls_offload_context_rx *priv_rx = wi->tls_set_params.priv_rx;
586 struct accel_rule *rule = &priv_rx->rule;
588 if (unlikely(test_bit(MLX5E_PRIV_RX_FLAG_DELETING, priv_rx->flags))) {
589 complete(&priv_rx->add_ctx);
609 struct mlx5e_ktls_offload_context_rx *priv_rx;
618 priv_rx = kzalloc(sizeof(*priv_rx), GFP_KERNEL);
619 if (unlikely(!priv_rx))
624 priv_rx->crypto_info.crypto_info_128 =
628 priv_rx->crypto_info.crypto_info_256 =
643 priv_rx->dek = dek;
645 INIT_LIST_HEAD(&priv_rx->list);
646 spin_lock_init(&priv_rx->lock);
649 priv_rx->rxq = rxq;
650 priv_rx->sk = sk;
652 priv_rx->rq_stats = &priv->channel_stats[rxq]->rq;
653 priv_rx->sw_stats = &priv->tls->sw_stats;
654 mlx5e_set_ktls_rx_priv_ctx(tls_ctx, priv_rx);
656 err = mlx5e_rx_res_tls_tir_create(priv->rx_res, rxq, &priv_rx->tir);
660 init_completion(&priv_rx->add_ctx);
662 accel_rule_init(&priv_rx->rule, priv);
663 resync = &priv_rx->resync;
668 err = post_rx_param_wqes(priv->channels.c[rxq], priv_rx, start_offload_tcp_sn);
672 atomic64_inc(&priv_rx->sw_stats->rx_tls_ctx);
677 mlx5e_tir_destroy(&priv_rx->tir);
679 mlx5_ktls_destroy_key(priv->tls->dek_pool, priv_rx->dek);
681 kfree(priv_rx);
687 struct mlx5e_ktls_offload_context_rx *priv_rx;
693 priv_rx = mlx5e_get_ktls_rx_priv_ctx(tls_ctx);
694 set_bit(MLX5E_PRIV_RX_FLAG_DELETING, priv_rx->flags);
697 if (!cancel_work_sync(&priv_rx->rule.work))
698 /* completion is needed, as the priv_rx in the add flow
701 wait_for_completion(&priv_rx->add_ctx);
702 resync = &priv_rx->resync;
704 mlx5e_ktls_priv_rx_put(priv_rx);
706 atomic64_inc(&priv_rx->sw_stats->rx_tls_del);
707 if (priv_rx->rule.rule)
708 mlx5e_accel_fs_del_sk(priv_rx->rule.rule);
710 mlx5e_tir_destroy(&priv_rx->tir);
711 mlx5_ktls_destroy_key(priv->tls->dek_pool, priv_rx->dek);
712 /* priv_rx should normally be freed here, but if there is an outstanding
716 mlx5e_ktls_priv_rx_put(priv_rx);
721 struct mlx5e_ktls_offload_context_rx *priv_rx, *tmp;
738 list_for_each_entry_safe(priv_rx, tmp, &ktls_resync->list, list) {
739 list_move(&priv_rx->list, &local_list);
751 priv_rx = list_first_entry(&local_list,
754 spin_lock(&priv_rx->lock);
755 cseg = post_static_params(sq, priv_rx);
757 spin_unlock(&priv_rx->lock);
760 list_del_init(&priv_rx->list);
761 spin_unlock(&priv_rx->lock);
768 priv_rx->rq_stats->tls_resync_res_ok += j;
779 priv_rx->rq_stats->tls_resync_res_retry++;