Lines Matching defs:eseg
76 struct mlx5_wqe_eth_seg *eseg, u8 mode,
93 eseg->swp_outer_l3_offset = skb_network_offset(skb) / 2;
95 eseg->swp_flags |= MLX5_ETH_WQE_SWP_OUTER_L3_IPV6;
99 eseg->swp_inner_l3_offset = skb_inner_network_offset(skb) / 2;
101 eseg->swp_flags |= MLX5_ETH_WQE_SWP_INNER_L3_IPV6;
105 eseg->swp_flags |= MLX5_ETH_WQE_SWP_INNER_L4_UDP;
109 eseg->swp_inner_l4_offset = skb_inner_transport_offset(skb) / 2;
124 eseg->swp_flags |= MLX5_ETH_WQE_SWP_OUTER_L4_UDP;
128 eseg->swp_outer_l4_offset = skb_inner_transport_offset(skb) / 2;
137 eseg->swp_flags |= MLX5_ETH_WQE_SWP_INNER_L4_UDP;
140 eseg->swp_inner_l3_offset = skb_inner_network_offset(skb) / 2;
141 eseg->swp_inner_l4_offset =
144 eseg->swp_flags |= MLX5_ETH_WQE_SWP_INNER_L3_IPV6;
220 struct mlx5_wqe_eth_seg *eseg)
241 mlx5e_ipsec_set_swp(skb, eseg, x->props.mode, xo);
247 eseg->flow_table_metadata |= cpu_to_be32(MLX5_ETH_WQE_FT_META_IPSEC);
248 eseg->trailer |= cpu_to_be32(MLX5_ETH_WQE_INSERT_TRAILER);
251 eseg->trailer |= (l3_proto == IPPROTO_ESP) ?
255 eseg->trailer |= (l3_proto == IPPROTO_ESP) ?