core/en/port.c

38 	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
44 	if (mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_EN, 1))
47 	*an_status = MLX5_GET(ptys_reg, out, an_status);
48 	*an_disable_cap = MLX5_GET(ptys_reg, out, an_disable_cap);
49 	*an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
55 	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
76 	return mlx5_core_access_reg(dev, in, sizeof(in), out,
77 			    sizeof(out), MLX5_REG_PTYS, 0, 1);
90 		goto out;
95 			goto out;
101 out:
105 int mlx5e_port_query_pbmc(struct mlx5_core_dev *mdev, void *out)
116 	err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PBMC, 0, 0);
125 	void *out;
128 	out = kzalloc(sz, GFP_KERNEL);
129 	if (!out)
133 	err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PBMC, 0, 1);
135 	kfree(out);
140 			  u8 pool_idx, void *out, int size_out)
148 	return mlx5_core_access_reg(mdev, in, sizeof(in), out, size_out, MLX5_REG_SBPR, 0, 0);
154 	u32 out[MLX5_ST_SZ_DW(sbpr_reg)] = {};
164 	return mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out), MLX5_REG_SBPR, 0, 1);
168 				 u8 pg_buff_idx, u8 dir, void *out,
178 	return mlx5_core_access_reg(mdev, in, sizeof(in), out, size_out, MLX5_REG_SBCM, 0, 0);
184 	u32 out[MLX5_ST_SZ_DW(sbcm_reg)] = {};
190 	err = mlx5e_port_query_sbcm(mdev, desc, pg_buff_idx, dir, out,
191 				    sizeof(out));
195 	exc = MLX5_GET(sbcm_reg, out, exc);
196 	min_buff = MLX5_GET(sbcm_reg, out, min_buff);
208 	return mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out), MLX5_REG_SBCM, 0, 1);
216 	void *out;
222 	out = kzalloc(sz, GFP_KERNEL);
223 	if (!in || !out) {
225 		goto out;
229 	err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPTB, 0, 0);
231 		goto out;
233 	prio_x_buff = MLX5_GET(pptb_reg, out, prio_x_buff);
238 out:
240 	kfree(out);
248 	void *out;
254 	out = kzalloc(sz, GFP_KERNEL);
255 	if (!in || !out) {
257 		goto out;
262 	err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPTB, 0, 0);
264 		goto out;
266 	memcpy(in, out, sz);
277 	err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPTB, 0, 1);
279 out:
281 	kfree(out);
432 	u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
442 	err =  mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PPLM, 0, 0);
452 		mlx5e_get_fec_cap_field(out, &fec_caps, i);
462 	u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
475 	err =  mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PPLM, 0, 0);
479 	*fec_mode_active = MLX5_GET(pplm_reg, out, fec_mode_active);
482 		goto out;
489 		mlx5e_fec_admin_field(out, fec_configured_mode, 0, i);
491 			goto out;
493 out:
500 	u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
520 	err = mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PPLM, 0, 0);
524 	MLX5_SET(pplm_reg, out, local_port, 1);
542 		mlx5e_get_fec_cap_field(out, &fec_caps, i);
546 			mlx5e_fec_admin_field(out, &conf_fec, 1, i);
549 			mlx5e_fec_admin_field(out, &fec_policy_auto, 1, i);
552 	return mlx5_core_access_reg(dev, out, sz, out, sz, MLX5_REG_PPLM, 0, 1);