Lines Matching refs:caps
299 dev->caps.reserved_uars =
311 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
312 for (i = 0; i < dev->caps.num_ports - 1; i++) {
320 for (i = 0; i < dev->caps.num_ports; i++) {
321 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
334 for (i = 1; i <= dev->caps.num_ports; ++i)
335 dev->caps.port_mask[i] = dev->caps.port_type[i];
347 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
363 struct mlx4_caps *dev_cap = &dev->caps;
399 dev->caps.vl_cap[port] = port_cap->max_vl;
400 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu;
406 dev->caps.gid_table_len[port] = port_cap->max_gids;
407 dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
408 dev->caps.port_width_cap[port] = port_cap->max_port_width;
409 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu;
410 dev->caps.max_tc_eth = port_cap->max_tc_eth;
411 dev->caps.def_mac[port] = port_cap->def_mac;
412 dev->caps.supported_type[port] = port_cap->supported_port_types;
413 dev->caps.suggested_type[port] = port_cap->suggested_type;
414 dev->caps.default_sense[port] = port_cap->default_sense;
415 dev->caps.trans_type[port] = port_cap->trans_type;
416 dev->caps.vendor_oui[port] = port_cap->vendor_oui;
417 dev->caps.wavelength[port] = port_cap->wavelength;
418 dev->caps.trans_code[port] = port_cap->trans_code;
438 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS))
443 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
447 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
450 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
487 dev->caps.num_ports = dev_cap->num_ports;
488 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
490 dev->caps.num_sys_eqs :
492 for (i = 1; i <= dev->caps.num_ports; ++i) {
500 dev->caps.map_clock_to_user = dev_cap->map_clock_to_user;
501 dev->caps.uar_page_size = PAGE_SIZE;
502 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
503 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
504 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
505 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
506 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
507 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
508 dev->caps.max_wqes = dev_cap->max_qp_sz;
509 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
510 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
511 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
512 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
513 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
514 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
519 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
520 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
521 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
522 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
523 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
525 dev->caps.reserved_pds = dev_cap->reserved_pds;
526 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
528 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
530 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
532 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
533 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
534 dev->caps.flags = dev_cap->flags;
535 dev->caps.flags2 = dev_cap->flags2;
536 dev->caps.bmme_flags = dev_cap->bmme_flags;
537 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
538 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
539 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
540 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
541 dev->caps.wol_port[1] = dev_cap->wol_port[1];
542 dev->caps.wol_port[2] = dev_cap->wol_port[2];
543 dev->caps.health_buffer_addrs = dev_cap->health_buffer_addrs;
558 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) {
570 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN;
575 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
578 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
581 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC;
582 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
584 dev->caps.log_num_macs = log_num_mac;
585 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
588 for (i = 1; i <= dev->caps.num_ports; ++i) {
589 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
590 if (dev->caps.supported_type[i]) {
592 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
593 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
595 else if (dev->caps.supported_type[i] ==
597 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
603 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
606 dev->caps.port_type[i] = port_type_array[i - 1];
616 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
617 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
618 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
625 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
627 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
630 dev->caps.port_type[i] = sensed_port;
632 dev->caps.possible_type[i] = dev->caps.port_type[i];
635 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
636 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
638 i, 1 << dev->caps.log_num_macs);
640 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
641 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
643 i, 1 << dev->caps.log_num_vlans);
647 if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) &&
652 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP;
655 dev->caps.max_counters = dev_cap->max_counters;
657 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
658 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
659 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
660 (1 << dev->caps.log_num_macs) *
661 (1 << dev->caps.log_num_vlans) *
662 dev->caps.num_ports;
663 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
666 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
667 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
669 dev->caps.dmfs_high_rate_qpn_base =
670 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
673 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
674 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
675 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
676 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
678 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
679 dev->caps.dmfs_high_rate_qpn_base =
680 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
681 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
684 dev->caps.rl_caps = dev_cap->rl_caps;
686 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
687 dev->caps.dmfs_high_rate_qpn_range;
689 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
690 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
691 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
692 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
694 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
700 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
701 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
713 if ((dev->caps.flags &
716 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
720 dev->caps.alloc_res_qp_mask =
721 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
724 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) &&
725 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
728 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
732 dev->caps.alloc_res_qp_mask = 0;
845 dev->caps.steering_mode = hca_param->steering_mode;
846 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
847 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
848 dev->caps.fs_log_max_ucast_qp_range_size =
851 dev->caps.num_qp_per_mgm =
855 mlx4_steering_mode_str(dev->caps.steering_mode));
860 kfree(dev->caps.spec_qps);
861 dev->caps.spec_qps = NULL;
867 struct mlx4_caps *caps = &dev->caps;
871 caps->spec_qps = kcalloc(caps->num_ports, sizeof(*caps->spec_qps), GFP_KERNEL);
873 if (!func_cap || !caps->spec_qps) {
879 for (i = 1; i <= caps->num_ports; ++i) {
886 caps->spec_qps[i - 1] = func_cap->spec_qps;
887 caps->port_mask[i] = caps->port_type[i];
888 caps->phys_port_id[i] = func_cap->phys_port_id;
890 &caps->gid_table_len[i],
891 &caps->pkey_table_len[i]);
938 dev->caps.hca_core_clock = hca_param->hca_core_clock;
940 dev->caps.max_qp_dest_rdma = 1 << hca_param->log_rd_per_qp;
951 page_size = ~dev->caps.page_size_cap + 1;
978 dev->caps.uar_page_size = PAGE_SIZE;
996 dev->caps.num_ports = func_cap->num_ports;
1002 dev->caps.num_qps = 1 << hca_param->log_num_qps;
1003 dev->caps.num_srqs = 1 << hca_param->log_num_srqs;
1004 dev->caps.num_cqs = 1 << hca_param->log_num_cqs;
1005 dev->caps.num_mpts = 1 << hca_param->log_mpt_sz;
1006 dev->caps.num_eqs = func_cap->max_eq;
1007 dev->caps.reserved_eqs = func_cap->reserved_eq;
1008 dev->caps.reserved_lkey = func_cap->reserved_lkey;
1009 dev->caps.num_pds = MLX4_NUM_PDS;
1010 dev->caps.num_mgms = 0;
1011 dev->caps.num_amgms = 0;
1013 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
1015 dev->caps.num_ports, MLX4_MAX_PORTS);
1024 mlx4_err(dev, "Set special QP caps failed. aborting\n");
1028 if (dev->caps.uar_page_size * (dev->caps.num_uars -
1029 dev->caps.reserved_uars) >
1033 dev->caps.uar_page_size * dev->caps.num_uars,
1041 dev->caps.eqe_size = 64;
1042 dev->caps.eqe_factor = 1;
1044 dev->caps.eqe_size = 32;
1045 dev->caps.eqe_factor = 0;
1049 dev->caps.cqe_size = 64;
1050 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1052 dev->caps.cqe_size = 32;
1056 dev->caps.eqe_size = hca_param->eqe_size;
1057 dev->caps.eqe_factor = 0;
1061 dev->caps.cqe_size = hca_param->cqe_size;
1063 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1066 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1069 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_USER_MAC_EN;
1077 dev->caps.bf_reg_size)
1078 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
1081 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
1104 for (port = 0; port < dev->caps.num_ports; port++) {
1107 if (port_types[port] != dev->caps.port_type[port + 1])
1112 for (port = 1; port <= dev->caps.num_ports; port++) {
1114 dev->caps.port_type[port] = port_types[port - 1];
1144 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1146 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1164 if ((port_type & mdev->caps.supported_type[info->port]) != port_type) {
1176 mdev->caps.possible_type[info->port] = info->tmp_type;
1178 for (i = 0; i < mdev->caps.num_ports; i++) {
1180 mdev->caps.possible_type[i+1];
1182 types[i] = mdev->caps.port_type[i+1];
1185 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1186 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
1187 for (i = 1; i <= mdev->caps.num_ports; i++) {
1188 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1189 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1208 for (i = 0; i < mdev->caps.num_ports; i++)
1293 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1297 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1311 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1325 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1330 for (port = 1; port <= mdev->caps.num_ports; port++) {
1378 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1483 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP))
1619 cmpt_entry_sz, dev->caps.num_qps,
1620 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1629 cmpt_entry_sz, dev->caps.num_srqs,
1630 dev->caps.reserved_srqs, 0, 0);
1638 cmpt_entry_sz, dev->caps.num_cqs,
1639 dev->caps.reserved_cqs, 0, 0);
1718 * dev->caps.mtt_entry_sz below is really the MTT segment
1721 dev->caps.reserved_mtts =
1722 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1723 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1727 dev->caps.mtt_entry_sz,
1728 dev->caps.num_mtts,
1729 dev->caps.reserved_mtts, 1, 0);
1738 dev->caps.num_mpts,
1739 dev->caps.reserved_mrws, 1, 1);
1748 dev->caps.num_qps,
1749 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1759 dev->caps.num_qps,
1760 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1770 dev->caps.num_qps,
1771 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1781 dev->caps.num_qps,
1782 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1792 dev->caps.num_cqs,
1793 dev->caps.reserved_cqs, 0, 0);
1802 dev->caps.num_srqs,
1803 dev->caps.reserved_srqs, 0, 0);
1819 dev->caps.num_mgms + dev->caps.num_amgms,
1820 dev->caps.num_mgms + dev->caps.num_amgms,
1912 if (!dev->caps.bf_reg_size)
1916 (dev->caps.num_uars << PAGE_SHIFT);
1918 (dev->caps.num_uars << PAGE_SHIFT);
1977 if (!dev->caps.map_clock_to_user) {
2070 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
2147 for (i = 1; i <= dev->caps.num_ports; i++) {
2148 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
2149 dev->caps.gid_table_len[i] =
2152 dev->caps.gid_table_len[i] = 1;
2153 dev->caps.pkey_table_len[i] =
2201 if (dev->caps.dmfs_high_steer_mode ==
2205 dev->caps.dmfs_high_steer_mode =
2219 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
2220 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
2221 dev->caps.fs_log_max_ucast_qp_range_size =
2224 if (dev->caps.dmfs_high_steer_mode !=
2226 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
2227 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
2228 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2229 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
2231 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
2233 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
2234 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2241 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
2244 mlx4_steering_mode_str(dev->caps.steering_mode),
2252 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2254 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
2256 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
2258 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
2267 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2270 for (i = 1; i <= dev->caps.num_ports; i++) {
2274 } else if ((dev->caps.dmfs_high_steer_mode !=
2277 !!(dev->caps.dmfs_high_steer_mode ==
2282 dev->caps.dmfs_high_steer_mode),
2351 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
2353 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
2368 if (dev->caps.steering_mode ==
2380 init_hca->log_uar_sz = ilog2(dev->caps.num_uars) +
2384 init_hca->log_uar_sz = ilog2(dev->caps.num_uars);
2389 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2390 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
2409 dev->caps.num_eqs = dev_cap->max_eqs;
2410 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2411 dev->caps.reserved_uars = dev_cap->reserved_uars;
2419 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2423 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2425 dev->caps.hca_core_clock =
2432 if (!dev->caps.hca_core_clock) {
2433 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2441 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2446 if (dev->caps.dmfs_high_steer_mode !=
2451 if (dev->caps.dmfs_high_steer_mode ==
2453 dev->caps.dmfs_high_rate_qpn_base =
2454 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
2455 dev->caps.dmfs_high_rate_qpn_range =
2461 dev->caps.dmfs_high_steer_mode));
2473 mlx4_err(dev, "Failed to obtain slave caps\n");
2496 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2497 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2534 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2537 if (!dev->caps.max_counters)
2540 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
2544 nent_pow2 - dev->caps.max_counters + 1);
2549 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2552 if (!dev->caps.max_counters)
2563 for (port = 0; port < dev->caps.num_ports; port++)
2574 for (port = 0; port < dev->caps.num_ports; port++)
2577 for (port = 0; port < dev->caps.num_ports; port++) {
2609 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2662 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2847 for (port = 1; port <= dev->caps.num_ports; port++) {
2852 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2854 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2868 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2870 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
2873 dev->caps.pkey_table_len[port] : -1);
2938 if (eqn > dev->caps.num_comp_vectors)
2968 int nreq = min3(dev->caps.num_ports *
2970 dev->caps.num_eqs - dev->caps.reserved_eqs,
2991 dev->caps.num_comp_vectors = nreq - 1;
2995 dev->caps.num_ports);
2997 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) {
3004 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) {
3006 dev->caps.num_ports);
3018 * (dev->caps.num_comp_vectors / dev->caps.num_ports)
3026 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) &&
3028 (dev->caps.num_comp_vectors / dev->caps.num_ports)) ==
3030 /* If dev->caps.num_comp_vectors < dev->caps.num_ports,
3043 dev->caps.num_comp_vectors = 1;
3050 dev->caps.num_ports);
3100 dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
3103 dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
3181 int num_entries = dev->caps.num_ports;
3202 int num_entries = dev->caps.num_ports;
3617 if (dev->caps.num_ports < 2 &&
3622 dev->caps.num_ports);
3635 dev->caps.num_ports;
3676 dev->caps.num_comp_vectors = 1;
3696 for (port = 1; port <= dev->caps.num_ports; port++) {
4109 for (i = 0; i < dev->caps.num_ports; i++) {
4110 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1];
4111 dev->persist->curr_port_poss_type[i] = dev->caps.
4120 for (p = 1; p <= dev->caps.num_ports; p++) {
4236 for (i = 0; i < dev->caps.num_ports; i++)
4237 dev->caps.possible_type[i + 1] = poss_types[i];