mellanox/mlx4/fw.c

490 		if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) ||
832 	dev_cap->flags2 = 0;
886 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
888 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
891 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
905 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN;
908 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
911 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER;
914 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_BEACON;
917 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
922 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT;
925 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN;
930 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
963 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_USER_MAC_EN;
966 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP;
1015 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QOS_VPP;
1017 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL;
1019 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
1021 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
1025 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ROCE_V1_V2;
1027 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP;
1030 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV;
1032 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
1035 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PHV_EN;
1037 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN;
1043 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP;
1045 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT;
1047 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW;
1050 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT;
1053 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
1056 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;
1058 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
1068 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;
1080 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT;
1094 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
1096 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB;
1098 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_LB_SRC_CHK;
1100 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
1102 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
1104 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS;
1106 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SW_CQ_INIT;
1123 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS;
1174 	if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) {
1183 	dump_dev_cap_flags2(dev, dev_cap->flags2);
1921 	if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG && enable_qos)
1951 	if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) &&
1952 	    (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) {
1964 	if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT)
1967 	if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW) {
2053 	if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) {
2488 	if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV))
2844 	if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX))
3036 	context->flags2 |=  SET_PORT_GEN_PHV_VALID;
3069 	if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN &&
3070 	    !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) {