mellanox/mlx4/fw.c

725 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
832 	dev_cap->flags2 = 0;
846 	dev_cap->map_clock_to_user = field & 0x80;
848 	dev_cap->reserved_qps = 1 << (field & 0xf);
850 	dev_cap->max_qps = 1 << (field & 0x1f);
852 	dev_cap->reserved_srqs = 1 << (field >> 4);
854 	dev_cap->max_srqs = 1 << (field & 0x1f);
856 	dev_cap->max_cq_sz = 1 << field;
858 	dev_cap->reserved_cqs = 1 << (field & 0xf);
860 	dev_cap->max_cqs = 1 << (field & 0x1f);
862 	dev_cap->max_mpts = 1 << (field & 0x3f);
864 	dev_cap->reserved_eqs = 1 << (field & 0xf);
866 	dev_cap->max_eqs = 1 << (field & 0xf);
868 	dev_cap->reserved_mtts = 1 << (field >> 4);
870 	dev_cap->reserved_mrws = 1 << (field & 0xf);
872 	dev_cap->num_sys_eqs = size & 0xfff;
874 	dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
876 	dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
880 		dev_cap->max_gso_sz = 0;
882 		dev_cap->max_gso_sz = 1 << field;
886 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
888 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
891 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
892 		dev_cap->max_rss_tbl_sz = 1 << field;
894 		dev_cap->max_rss_tbl_sz = 0;
896 	dev_cap->max_rdma_global = 1 << (field & 0x3f);
898 	dev_cap->local_ca_ack_delay = field & 0x1f;
900 	dev_cap->num_ports = field & 0xf;
902 	dev_cap->max_msg_sz = 1 << (field & 0x1f);
905 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN;
908 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
909 	dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
911 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER;
914 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_BEACON;
917 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
919 	dev_cap->fs_max_num_qp_per_entry = field;
922 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT;
925 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN;
927 	dev_cap->stat_rate_support = stat_rate;
930 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
933 	dev_cap->flags = flags | (u64)ext_flags << 32;
935 	dev_cap->wol_port[1] = !!(field & 0x20);
936 	dev_cap->wol_port[2] = !!(field & 0x40);
938 	dev_cap->reserved_uars = field >> 4;
940 	dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
942 	dev_cap->min_page_sz = 1 << field;
947 		dev_cap->bf_reg_size = 1 << (field & 0x1f);
949 		if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
951 		dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
953 		dev_cap->bf_reg_size = 0;
957 	dev_cap->max_sq_sg = field;
959 	dev_cap->max_sq_desc_sz = size;
963 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_USER_MAC_EN;
966 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP;
968 	dev_cap->max_qp_per_mcg = 1 << field;
970 	dev_cap->reserved_mgms = field & 0xf;
972 	dev_cap->max_mcgs = 1 << field;
974 	dev_cap->reserved_pds = field >> 4;
976 	dev_cap->max_pds = 1 << (field & 0x3f);
978 	dev_cap->reserved_xrcds = field >> 4;
980 	dev_cap->max_xrcds = 1 << (field & 0x1f);
983 	dev_cap->rdmarc_entry_sz = size;
985 	dev_cap->qpc_entry_sz = size;
987 	dev_cap->aux_entry_sz = size;
989 	dev_cap->altc_entry_sz = size;
991 	dev_cap->eqc_entry_sz = size;
993 	dev_cap->cqc_entry_sz = size;
995 	dev_cap->srq_entry_sz = size;
997 	dev_cap->cmpt_entry_sz = size;
999 	dev_cap->mtt_entry_sz = size;
1001 	dev_cap->dmpt_entry_sz = size;
1004 	dev_cap->max_srq_sz = 1 << field;
1006 	dev_cap->max_qp_sz = 1 << field;
1008 	dev_cap->resize_srq = field & 1;
1010 	dev_cap->max_rq_sg = field;
1012 	dev_cap->max_rq_desc_sz = size;
1015 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QOS_VPP;
1017 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL;
1019 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
1021 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
1022 	MLX4_GET(dev_cap->bmme_flags, outbox,
1024 	if (dev_cap->bmme_flags & MLX4_FLAG_ROCE_V1_V2)
1025 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ROCE_V1_V2;
1026 	if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP)
1027 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP;
1030 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV;
1032 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
1035 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PHV_EN;
1037 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN;
1039 	MLX4_GET(dev_cap->reserved_lkey, outbox,
1043 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP;
1045 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT;
1047 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW;
1050 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT;
1053 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
1056 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;
1058 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
1059 	MLX4_GET(dev_cap->max_icm_sz, outbox,
1061 	if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1062 		MLX4_GET(dev_cap->max_counters, outbox,
1068 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;
1070 	MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox,
1072 	dev_cap->dmfs_high_rate_qpn_base &= MGM_QPN_MASK;
1073 	MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox,
1075 	dev_cap->dmfs_high_rate_qpn_range &= MGM_QPN_MASK;
1078 	dev_cap->rl_caps.num_rates = size;
1079 	if (dev_cap->rl_caps.num_rates) {
1080 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT;
1082 		dev_cap->rl_caps.max_val  = size & 0xfff;
1083 		dev_cap->rl_caps.max_unit = size >> 14;
1085 		dev_cap->rl_caps.min_val  = size & 0xfff;
1086 		dev_cap->rl_caps.min_unit = size >> 14;
1089 	MLX4_GET(dev_cap->health_buffer_addrs, outbox,
1094 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
1096 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB;
1098 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_LB_SRC_CHK;
1100 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
1102 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
1104 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS;
1106 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SW_CQ_INIT;
1108 	for (i = 1; i <= dev_cap->num_ports; i++) {
1109 		err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i);
1119 	if (dev_cap->num_sys_eqs == 0)
1120 		dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
1121 					    dev_cap->reserved_eqs);
1123 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS;
1130 void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
1132 	if (dev_cap->bf_reg_size > 0)
1134 			 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
1139 		 dev_cap->bmme_flags, dev_cap->reserved_lkey);
1141 		 (unsigned long long) dev_cap->max_icm_sz >> 20);
1143 		 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
1145 		 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
1147 		 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
1149 		 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs,
1150 		 dev_cap->eqc_entry_sz);
1152 		 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
1154 		 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
1156 		 dev_cap->max_pds, dev_cap->reserved_mgms);
1158 		 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
1160 		 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu,
1161 		 dev_cap->port_cap[1].max_port_width);
1163 		 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
1165 		 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
1166 	mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
1167 	mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
1168 	mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
1170 		 dev_cap->dmfs_high_rate_qpn_base);
1172 		 dev_cap->dmfs_high_rate_qpn_range);
1174 	if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) {
1175 		struct mlx4_rate_limit_caps *rl_caps = &dev_cap->rl_caps;
1182 	dump_dev_cap_flags(dev, dev_cap->flags);
1183 	dump_dev_cap_flags2(dev, dev_cap->flags2);