mellanox/mlx4/fw.c

1109 		err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i);
1160 		 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu,
1161 		 dev_cap->port_cap[1].max_port_width);
1186 int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap)
1208 		port_cap->max_vl	   = field >> 4;
1210 		port_cap->ib_mtu	   = field >> 4;
1211 		port_cap->max_port_width = field & 0xf;
1213 		port_cap->max_gids	   = 1 << (field & 0xf);
1215 		port_cap->max_pkeys	   = 1 << (field & 0xf);
1235 		port_cap->link_state = (field & 0x80) >> 7;
1236 		port_cap->supported_port_types = field & 3;
1237 		port_cap->suggested_type = (field >> 3) & 1;
1238 		port_cap->default_sense = (field >> 4) & 1;
1239 		port_cap->dmfs_optimized_state = (field >> 5) & 1;
1241 		port_cap->ib_mtu	   = field & 0xf;
1243 		port_cap->max_port_width = field & 0xf;
1245 		port_cap->max_gids	   = 1 << (field >> 4);
1246 		port_cap->max_pkeys	   = 1 << (field & 0xf);
1248 		port_cap->max_vl	   = field & 0xf;
1249 		port_cap->max_tc_eth	   = field >> 4;
1251 		port_cap->log_max_macs  = field & 0xf;
1252 		port_cap->log_max_vlans = field >> 4;
1253 		MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET);
1254 		MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET);
1256 		port_cap->trans_type = field32 >> 24;
1257 		port_cap->vendor_oui = field32 & 0xffffff;
1258 		MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET);
1259 		MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET);
1461 			struct mlx4_port_cap port_cap;
1463 			err = mlx4_QUERY_PORT(dev, other_port, &port_cap);
1466 			port_type |= (port_cap.link_state << 7);