mellanox/mlx4/fw.c

209 	u8 field;
235 	MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET);
236 	func->bus = field & 0xf;
237 	MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET);
238 	func->device = field & 0xf1;
239 	MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET);
240 	func->function = field & 0x7;
241 	MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET);
242 	func->physical_function = field & 0xf;
247 	MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET);
248 	func->rsvd_uars = field & 0x0f;
332 	u8	field, port;
406 		field = vhcr->in_modifier -
408 		MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
414 		field  = QUERY_FUNC_CAP_FLAGS1_NIC_INFO;
418 			field |= QUERY_FUNC_CAP_VF_ENABLE_QP0;
422 		MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);
443 		field = 0;
445 			field |= QUERY_FUNC_CAP_PHV_BIT;
447 			field |= QUERY_FUNC_CAP_VLAN_OFFLOAD_DISABLE;
448 		MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS0_OFFSET);
459 		field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
462 		MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
464 		field = min(
467 		MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
472 		field = 0; /* protected FMR support not available as yet */
473 		MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
544 	u8			field, op_modifier;
568 		MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
569 		if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
574 		func_cap->flags = field;
577 		MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
578 		func_cap->num_ports = field;
670 		MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
671 		if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {
678 	MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
679 	func_cap->physical_port = field;
729 	u8 field;
845 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAP_CLOCK_TO_USER);
846 	dev_cap->map_clock_to_user = field & 0x80;
847 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
848 	dev_cap->reserved_qps = 1 << (field & 0xf);
849 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
850 	dev_cap->max_qps = 1 << (field & 0x1f);
851 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
852 	dev_cap->reserved_srqs = 1 << (field >> 4);
853 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
854 	dev_cap->max_srqs = 1 << (field & 0x1f);
855 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
856 	dev_cap->max_cq_sz = 1 << field;
857 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
858 	dev_cap->reserved_cqs = 1 << (field & 0xf);
859 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
860 	dev_cap->max_cqs = 1 << (field & 0x1f);
861 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
862 	dev_cap->max_mpts = 1 << (field & 0x3f);
863 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
864 	dev_cap->reserved_eqs = 1 << (field & 0xf);
865 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
866 	dev_cap->max_eqs = 1 << (field & 0xf);
867 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
868 	dev_cap->reserved_mtts = 1 << (field >> 4);
869 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
870 	dev_cap->reserved_mrws = 1 << (field & 0xf);
873 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
874 	dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
875 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
876 	dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
877 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
878 	field &= 0x1f;
879 	if (!field)
882 		dev_cap->max_gso_sz = 1 << field;
884 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
885 	if (field & 0x20)
887 	if (field & 0x10)
889 	field &= 0xf;
890 	if (field) {
892 		dev_cap->max_rss_tbl_sz = 1 << field;
895 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
896 	dev_cap->max_rdma_global = 1 << (field & 0x3f);
897 	MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
898 	dev_cap->local_ca_ack_delay = field & 0x1f;
899 	MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
900 	dev_cap->num_ports = field & 0xf;
901 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
902 	dev_cap->max_msg_sz = 1 << (field & 0x1f);
903 	MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET);
904 	if (field & 0x10)
906 	MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
907 	if (field & 0x80)
909 	dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
910 	if (field & 0x20)
912 	MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_BEACON_OFFSET);
913 	if (field & 0x80)
915 	MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
916 	if (field & 0x80)
918 	MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
919 	dev_cap->fs_max_num_qp_per_entry = field;
920 	MLX4_GET(field, outbox, QUERY_DEV_CAP_SL2VL_EVENT_OFFSET);
921 	if (field & (1 << 5))
923 	MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
924 	if (field & 0x1)
928 	MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
929 	if (field & 0x80)
934 	MLX4_GET(field, outbox, QUERY_DEV_CAP_WOL_OFFSET);
935 	dev_cap->wol_port[1] = !!(field & 0x20);
936 	dev_cap->wol_port[2] = !!(field & 0x40);
937 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
938 	dev_cap->reserved_uars = field >> 4;
939 	MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
940 	dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
941 	MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
942 	dev_cap->min_page_sz = 1 << field;
944 	MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
945 	if (field & 0x80) {
946 		MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
947 		dev_cap->bf_reg_size = 1 << (field & 0x1f);
948 		MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
949 		if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
950 			field = 3;
951 		dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
956 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
957 	dev_cap->max_sq_sg = field;
961 	MLX4_GET(field, outbox, QUERY_DEV_CAP_USER_MAC_EN_OFFSET);
962 	if (field & (1 << 2))
964 	MLX4_GET(field, outbox, QUERY_DEV_CAP_SVLAN_BY_QP_OFFSET);
965 	if (field & 0x1)
967 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
968 	dev_cap->max_qp_per_mcg = 1 << field;
969 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
970 	dev_cap->reserved_mgms = field & 0xf;
971 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
972 	dev_cap->max_mcgs = 1 << field;
973 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
974 	dev_cap->reserved_pds = field >> 4;
975 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
976 	dev_cap->max_pds = 1 << (field & 0x3f);
977 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
978 	dev_cap->reserved_xrcds = field >> 4;
979 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
980 	dev_cap->max_xrcds = 1 << (field & 0x1f);
1003 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
1004 	dev_cap->max_srq_sz = 1 << field;
1005 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
1006 	dev_cap->max_qp_sz = 1 << field;
1007 	MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
1008 	dev_cap->resize_srq = field & 1;
1009 	MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
1010 	dev_cap->max_rq_sg = field;
1013 	MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
1014 	if (field & (1 << 4))
1016 	if (field & (1 << 5))
1018 	if (field & (1 << 6))
1020 	if (field & (1 << 7))
1028 	MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
1029 	if (field & 0x20)
1031 	if (field & (1 << 2))
1033 	MLX4_GET(field, outbox, QUERY_DEV_CAP_PHV_EN_OFFSET);
1034 	if (field & 0x80)
1036 	if (field & 0x40)
1051 	MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
1052 	if (field & 1<<6)
1054 	MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);
1055 	if (field & 1<<3)
1057 	if (field & (1 << 5))
1190 	u8 field;
1207 		MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
1208 		port_cap->max_vl	   = field >> 4;
1209 		MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
1210 		port_cap->ib_mtu	   = field >> 4;
1211 		port_cap->max_port_width = field & 0xf;
1212 		MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
1213 		port_cap->max_gids	   = 1 << (field & 0xf);
1214 		MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
1215 		port_cap->max_pkeys	   = 1 << (field & 0xf);
1234 		MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1235 		port_cap->link_state = (field & 0x80) >> 7;
1236 		port_cap->supported_port_types = field & 3;
1237 		port_cap->suggested_type = (field >> 3) & 1;
1238 		port_cap->default_sense = (field >> 4) & 1;
1239 		port_cap->dmfs_optimized_state = (field >> 5) & 1;
1240 		MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
1241 		port_cap->ib_mtu	   = field & 0xf;
1242 		MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
1243 		port_cap->max_port_width = field & 0xf;
1244 		MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
1245 		port_cap->max_gids	   = 1 << (field >> 4);
1246 		port_cap->max_pkeys	   = 1 << (field & 0xf);
1247 		MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
1248 		port_cap->max_vl	   = field & 0xf;
1249 		port_cap->max_tc_eth	   = field >> 4;
1250 		MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
1251 		port_cap->log_max_macs  = field & 0xf;
1252 		port_cap->log_max_vlans = field >> 4;
1280 	u8	field;
1318 	MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET);
1319 	field &= ~0x0F;
1320 	field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F;
1321 	MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET);
1324 	MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1325 	field &= 0x7f;
1326 	MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1329 	MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN);
1330 	field &= 0xd7;
1331 	MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN);
1334 	MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_PORT_BEACON_OFFSET);
1335 	field &= 0x7f;
1336 	MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_PORT_BEACON_OFFSET);
1339 	MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
1340 	field &= 0x7f;
1341 	MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
1351 		MLX4_GET(field, outbox->buf,
1353 		field &= 0x7f;
1354 		MLX4_PUT(outbox->buf, field,
1359 	MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
1360 	field &= ~0x80;
1361 	MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
1370 	MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
1371 	field &= 0xfe;
1372 	MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
1379 	MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
1380 	field &= 0xef;
1381 	MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
1384 	MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
1385 	field &= 0xfb;
1386 	MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
1492 	u16			field;
1507 	MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
1508 	*gid_tbl_len = field;
1510 	MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1511 	*pkey_tbl_len = field;
2302 	u16 field;
2329 		field = 128 << dev->caps.ib_mtu_cap[port];
2330 		MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
2331 		field = dev->caps.gid_table_len[port];
2332 		MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
2333 		field = dev->caps.pkey_table_len[port];
2334 		MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
2913  * field into reg_data or a negative error code.