Lines Matching refs:eq
97 static void eq_set_ci(struct mlx4_eq *eq, int req_not)
99 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
101 eq->doorbell);
106 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor,
109 /* (entry & (eq->nent - 1)) gives us a cyclic array */
110 unsigned long offset = (entry & (eq->nent - 1)) * eqe_size;
118 return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE;
121 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor, u8 size)
123 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor, size);
124 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
241 struct mlx4_eq *eq = &priv->eq_table.eq[vec];
243 if (!cpumask_available(eq->affinity_mask) ||
244 cpumask_empty(eq->affinity_mask))
247 hint_err = irq_update_affinity_hint(eq->irq, eq->affinity_mask);
494 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
512 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor, eqe_size))) {
543 eq->eqn, eq->cons_index, ret);
558 mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT. srq_no=0x%x, eq 0x%x\n",
560 eq->eqn);
573 eq->eqn, eq->cons_index, ret);
698 eq->eqn, eq->cons_index, ret);
714 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
782 eqe->type, eqe->subtype, eq->eqn,
783 eq->cons_index, eqe->owner, eq->nent,
786 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
807 eqe->type, eqe->subtype, eq->eqn,
808 eq->cons_index, eqe->owner, eq->nent,
810 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
819 eqe->type, eqe->subtype, eq->eqn,
820 eq->cons_index, eqe->owner, eq->nent,
823 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
827 ++eq->cons_index;
839 eq_set_ci(eq, 0);
844 eq_set_ci(eq, 1);
859 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
866 struct mlx4_eq *eq = eq_ptr;
867 struct mlx4_dev *dev = eq->dev;
869 mlx4_eq_int(dev, eq);
935 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
940 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
946 ((eq->eqn / 4) << (dev->uar_page_shift)),
950 eq->eqn);
955 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
971 u8 intr, struct mlx4_eq *eq)
983 eq->dev = dev;
984 eq->nent = roundup_pow_of_two(max(nent, 2));
988 npages = PAGE_ALIGN(eq->nent * dev->caps.eqe_size) / PAGE_SIZE;
990 eq->page_list = kmalloc_array(npages, sizeof(*eq->page_list),
992 if (!eq->page_list)
996 eq->page_list[i].buf = NULL;
1008 eq->page_list[i].buf = dma_alloc_coherent(&dev->persist->
1012 if (!eq->page_list[i].buf)
1016 eq->page_list[i].map = t;
1019 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
1020 if (eq->eqn == -1)
1023 eq->doorbell = mlx4_get_eq_uar(dev, eq);
1024 if (!eq->doorbell) {
1029 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
1033 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
1039 eq_context->log_eq_size = ilog2(eq->nent);
1043 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
1047 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
1056 eq->cons_index = 0;
1058 INIT_LIST_HEAD(&eq->tasklet_ctx.list);
1059 INIT_LIST_HEAD(&eq->tasklet_ctx.process_list);
1060 spin_lock_init(&eq->tasklet_ctx.lock);
1061 tasklet_setup(&eq->tasklet_ctx.task, mlx4_cq_tasklet_cb);
1066 mlx4_mtt_cleanup(dev, &eq->mtt);
1069 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR);
1073 if (eq->page_list[i].buf)
1075 eq->page_list[i].buf,
1076 eq->page_list[i].map);
1081 kfree(eq->page_list);
1089 struct mlx4_eq *eq)
1097 int npages = PAGE_ALIGN(dev->caps.eqe_size * eq->nent) / PAGE_SIZE;
1099 err = mlx4_HW2SW_EQ(dev, eq->eqn);
1103 synchronize_irq(eq->irq);
1104 tasklet_disable(&eq->tasklet_ctx.task);
1106 mlx4_mtt_cleanup(dev, &eq->mtt);
1109 eq->page_list[i].buf,
1110 eq->page_list[i].map);
1112 kfree(eq->page_list);
1113 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR);
1125 if (eq_table->eq[i].have_irq) {
1126 free_cpumask_var(eq_table->eq[i].affinity_mask);
1127 irq_update_affinity_hint(eq_table->eq[i].irq, NULL);
1128 free_irq(eq_table->eq[i].irq, eq_table->eq + i);
1129 eq_table->eq[i].have_irq = 0;
1161 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
1162 sizeof(*priv->eq_table.eq), GFP_KERNEL);
1163 if (!priv->eq_table.eq)
1171 kfree(mlx4_priv(dev)->eq_table.eq);
1224 0, &priv->eq_table.eq[MLX4_EQ_ASYNC]);
1226 struct mlx4_eq *eq = &priv->eq_table.eq[i];
1228 int port = find_first_bit(eq->actv_ports.ports,
1246 info->rmap, eq->irq);
1255 eq);
1272 err = request_irq(priv->eq_table.eq[MLX4_EQ_ASYNC].irq,
1274 priv->eq_table.eq + MLX4_EQ_ASYNC);
1278 priv->eq_table.eq[MLX4_EQ_ASYNC].have_irq = 1;
1293 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn);
1296 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn, err);
1298 /* arm ASYNC eq */
1299 eq_set_ci(&priv->eq_table.eq[MLX4_EQ_ASYNC], 1);
1305 mlx4_free_eq(dev, &priv->eq_table.eq[--i]);
1336 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn);
1349 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1381 /* Map the new eq to handle all asynchronous events */
1383 priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(vector)].eqn);
1385 mlx4_warn(dev, "Failed mapping eq for interrupt test\n");
1397 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn);
1413 return test_bit(port - 1, priv->eq_table.eq[vector].actv_ports.ports);
1425 priv->eq_table.eq[i].actv_ports.ports);
1439 return !!(bitmap_weight(priv->eq_table.eq[vector].actv_ports.ports,
1464 priv->eq_table.eq[requested_vector].actv_ports.ports)) {
1467 struct mlx4_eq *eq;
1473 eq = &priv->eq_table.eq[requested_vector];
1475 test_bit(port - 1, eq->actv_ports.ports)) {
1485 struct mlx4_eq *eq = &priv->eq_table.eq[i];
1487 if (min_ref_count_val > eq->ref_count &&
1488 test_bit(port - 1, eq->actv_ports.ports)) {
1489 min_ref_count_val = eq->ref_count;
1510 err = request_irq(priv->eq_table.eq[*prequested_vector].irq,
1513 priv->eq_table.eq + *prequested_vector);
1522 eq_set_ci(&priv->eq_table.eq[*prequested_vector], 1);
1523 priv->eq_table.eq[*prequested_vector].have_irq = 1;
1528 priv->eq_table.eq[*prequested_vector].ref_count++;
1546 return priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(cq_vec)].irq;
1556 priv->eq_table.eq[eq_vec].ref_count--;