ethernet/mediatek/mtk_wed.c

93 wed_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val)
95 	regmap_update_bits(dev->hw->regs, reg, mask | val, val);
111 wdma_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val)
113 	wdma_w32(dev, reg, (wdma_r32(dev, reg) & ~mask) | val);
135 wifi_w32(struct mtk_wed_device *dev, u32 reg, u32 val)
137 	writel(val, dev->wlan.base + reg);
274 	u32 val;
276 	return read_poll_timeout(mtk_wed_check_busy, val, !val, sleep,
401 	u32 val;
411 	if (readx_poll_timeout(mtk_wed_wo_read_status, dev, val,
412 			       val == MTK_WED_WOIF_DISABLE_DONE,
418 	val = readl(reg);
421 		val |= MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK;
422 		writel(val, reg);
423 		val &= ~MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK;
424 		writel(val, reg);
427 		val |= MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK;
428 		writel(val, reg);
429 		val &= ~MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK;
430 		writel(val, reg);
1565 	u8 val = MTK_WED_WO_STATE_SER_RESET;
1569 				   MTK_WED_WO_CMD_CHANGE_STATE, &val,
1570 				   sizeof(val), true);
1703 	val = MTK_WED_WO_STATE_ENABLE;
1705 				   MTK_WED_WO_CMD_CHANGE_STATE, &val,
1706 				   sizeof(val), true);
1728 	u32 val;
1754 		val = MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE |
1756 		val &= ~MTK_WED_WDMA_GLO_CFG_RX_DRV_EN;
1757 		wed_w32(dev, MTK_WED_WDMA_GLO_CFG, val);
1804 			val = FIELD_GET(MTK_WED_TX_BM_INTF_TKFIFO_FDEP,
1807 			val = FIELD_GET(MTK_WED_TX_TKID_INTF_TKFIFO_FDEP,
1809 		if (val == 0x40)
2141 		u32 val;
2152 		val = wifi_r32(dev,
2157 			 val);
2266 	u32 val = readl(regs + MTK_WED_RING_OFS_COUNT);
2295 		val = wed_r32(dev, MTK_WED_ADDR_ELEM_TBL_CFG);
2296 		while (!(val & MTK_WED_ADDR_ELEM_TBL_WR_RDY) && count++ < 100)
2297 			val = wed_r32(dev, MTK_WED_ADDR_ELEM_TBL_CFG);
2312 		val = wed_r32(dev, MTK_WED_PN_CHECK_CFG);
2313 		while (!(val & MTK_WED_PN_CHECK_WR_RDY) && count++ < 100)
2314 			val = wed_r32(dev, MTK_WED_PN_CHECK_CFG);
2344 		u32 val = dev->wlan.wpdma_phys | MTK_PCIE_MIRROR_MAP_EN |
2348 		val |= BIT(0) | (BIT(1) * !!dev->hw->index);
2349 		regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
2536 		u32 val = readl(regs + i);
2538 		wed_w32(dev, MTK_WED_RING_RX(index) + i, val);
2539 		wed_w32(dev, MTK_WED_WPDMA_RING_RX(index) + i, val);
2581 	u32 val, ext_mask;
2589 	val = wed_r32(dev, MTK_WED_EXT_INT_STATUS);
2590 	wed_w32(dev, MTK_WED_EXT_INT_STATUS, val);
2591 	val &= ext_mask;
2593 		val &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
2594 	if (val && net_ratelimit())
2595 		pr_err("mtk_wed%d: error status=%08x\n", dev->hw->index, val);
2597 	val = wed_r32(dev, MTK_WED_INT_STATUS);
2598 	val &= mask;
2599 	wed_w32(dev, MTK_WED_INT_STATUS, val); /* ACK */
2601 	return val;