Lines Matching refs:pf
56 struct otx2_nic *pf = netdev_priv(netdev);
60 if (pf->xdp_prog && new_mtu > MAX_XDP_MTU) {
78 static void otx2_disable_flr_me_intr(struct otx2_nic *pf)
80 int irq, vfs = pf->total_vfs;
83 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs));
84 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0);
85 free_irq(irq, pf);
88 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs));
89 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0);
90 free_irq(irq, pf);
95 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
96 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1);
97 free_irq(irq, pf);
99 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
100 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1);
101 free_irq(irq, pf);
104 static void otx2_flr_wq_destroy(struct otx2_nic *pf)
106 if (!pf->flr_wq)
108 destroy_workqueue(pf->flr_wq);
109 pf->flr_wq = NULL;
110 devm_kfree(pf->dev, pf->flr_wrk);
116 struct otx2_nic *pf = flrwork->pf;
117 struct mbox *mbox = &pf->mbox;
121 vf = flrwork - pf->flr_wrk;
132 if (!otx2_sync_mbox_msg(&pf->mbox)) {
138 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
139 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf));
147 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
151 if (pf->total_vfs > 64)
155 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg));
163 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work);
165 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf));
167 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg),
176 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
180 if (pf->total_vfs > 64)
184 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg));
191 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
193 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf));
199 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs)
201 struct otx2_hw *hw = &pf->hw;
207 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc));
208 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0),
209 otx2_pf_me_intr_handler, 0, irq_name, pf);
211 dev_err(pf->dev,
217 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc));
218 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0),
219 otx2_pf_flr_intr_handler, 0, irq_name, pf);
221 dev_err(pf->dev,
229 rvu_get_pf(pf->pcifunc));
231 (pf->pdev, RVU_PF_INT_VEC_VFME1),
232 otx2_pf_me_intr_handler, 0, irq_name, pf);
234 dev_err(pf->dev,
239 rvu_get_pf(pf->pcifunc));
241 (pf->pdev, RVU_PF_INT_VEC_VFFLR1),
242 otx2_pf_flr_intr_handler, 0, irq_name, pf);
244 dev_err(pf->dev,
251 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs));
252 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs));
255 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs));
256 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs));
261 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs));
262 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1),
265 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs));
266 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1),
272 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs)
276 pf->flr_wq = alloc_ordered_workqueue("otx2_pf_flr_wq", WQ_HIGHPRI);
277 if (!pf->flr_wq)
280 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs,
282 if (!pf->flr_wrk) {
283 destroy_workqueue(pf->flr_wq);
288 pf->flr_wrk[vf].pf = pf;
289 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler);
313 * when the interrupt handler is called. pf->mw[i].num_msgs
315 * pf->mw[i].up_num_msgs holds the data for use in
354 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf,
373 dst_mbox = &pf->mbox;
382 mutex_lock(&pf->mbox.lock);
393 dev_warn(pf->dev,
396 dst_mdev->mbase = pf->mbox.bbuf_base;
397 mutex_unlock(&pf->mbox.lock);
408 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox,
409 pf->mbox.bbuf_base, vf);
410 mutex_unlock(&pf->mbox.lock);
418 dst_mbox = &pf->mbox_pfvf[0];
431 dev_warn(pf->dev,
439 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf],
440 &pf->mbox.mbox_up,
441 pf->mbox_pfvf[vf].bbuf_base,
456 struct otx2_nic *pf;
459 pf = vf_mbox->pfvf;
460 vf_idx = vf_mbox - pf->mbox_pfvf;
462 mbox = &pf->mbox_pfvf[0].mbox;
480 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx,
494 struct otx2_nic *pf = vf_mbox->pfvf;
501 vf_idx = vf_mbox - pf->mbox_pfvf;
502 mbox = &pf->mbox_pfvf[0].mbox_up;
512 dev_err(pf->dev,
518 dev_err(pf->dev,
529 dev_err(pf->dev,
545 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq);
546 int vfs = pf->total_vfs;
550 mbox = pf->mbox_pfvf;
553 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1));
554 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr);
555 otx2_queue_vf_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr);
561 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0));
562 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr);
564 otx2_queue_vf_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr);
572 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs)
582 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs,
584 if (!pf->mbox_pfvf)
587 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox",
590 if (!pf->mbox_pfvf_wq)
596 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag))
597 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) +
600 base = readq((void __iomem *)((u64)pf->reg_base +
603 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs);
609 mbox = &pf->mbox_pfvf[0];
610 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base,
615 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base,
621 mbox->pfvf = pf;
633 destroy_workqueue(pf->mbox_pfvf_wq);
637 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf)
639 struct mbox *mbox = &pf->mbox_pfvf[0];
644 if (pf->mbox_pfvf_wq) {
645 destroy_workqueue(pf->mbox_pfvf_wq);
646 pf->mbox_pfvf_wq = NULL;
655 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
658 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull);
659 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull);
662 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs));
665 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1),
670 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
675 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull);
676 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull);
678 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull);
679 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0);
680 free_irq(vector, pf);
683 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull);
684 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1);
685 free_irq(vector, pf);
689 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
691 struct otx2_hw *hw = &pf->hw;
697 if (pf->pcifunc)
699 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc));
702 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0),
703 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf);
705 dev_err(pf->dev,
713 if (pf->pcifunc)
715 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc));
718 err = request_irq(pci_irq_vector(pf->pdev,
721 0, irq_name, pf);
723 dev_err(pf->dev,
729 otx2_enable_pfvf_mbox_intr(pf, numvfs);
734 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf,
740 dev_err(pf->dev,
746 dev_err(pf->dev,
755 struct otx2_vf_config *config = &pf->vf_configs[devid - 1];
774 pf->pcifunc = msg->pcifunc;
777 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg);
780 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg);
783 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg);
786 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg);
789 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg);
792 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg);
796 dev_err(pf->dev,
810 struct otx2_nic *pf;
821 pf = af_mbox->pfvf;
825 otx2_process_pfaf_mbox_msg(pf, msg);
834 static void otx2_handle_link_event(struct otx2_nic *pf)
836 struct cgx_link_user_info *linfo = &pf->linfo;
837 struct net_device *netdev = pf->netdev;
851 int otx2_mbox_up_handler_mcs_intr_notify(struct otx2_nic *pf,
855 cn10k_handle_mcs_event(pf, event);
860 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf,
867 pf->linfo = msg->link_info;
870 for (i = 0; i < pci_num_vf(pf->pdev); i++) {
871 struct otx2_vf_config *config = &pf->vf_configs[i];
881 if (pf->flags & OTX2_FLAG_INTF_DOWN)
884 otx2_handle_link_event(pf);
888 static int otx2_process_mbox_msg_up(struct otx2_nic *pf,
893 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id);
904 &pf->mbox.mbox_up, 0, \
915 pf, (struct _req_type *)req, rsp); \
923 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id);
934 struct otx2_nic *pf = af_mbox->pfvf;
951 otx2_process_mbox_msg_up(pf, msg);
955 if (devid && pci_num_vf(pf->pdev)) {
956 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up,
967 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
968 struct mbox *mw = &pf->mbox;
975 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0));
978 mbox_data = otx2_read64(pf, RVU_PF_PFAF_MBOX0);
982 otx2_write64(pf, RVU_PF_PFAF_MBOX0, mbox_data);
990 queue_work(pf->mbox_wq, &mw->mbox_up_wrk);
992 trace_otx2_msg_interrupt(pf->pdev, "UP message from AF to PF",
998 otx2_write64(pf, RVU_PF_PFAF_MBOX0, mbox_data);
1006 queue_work(pf->mbox_wq, &mw->mbox_wrk);
1008 trace_otx2_msg_interrupt(pf->pdev, "DOWN reply from AF to PF",
1015 static void otx2_disable_mbox_intr(struct otx2_nic *pf)
1017 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX);
1020 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0));
1021 free_irq(vector, pf);
1024 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af)
1026 struct otx2_hw *hw = &pf->hw;
1034 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX),
1035 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf);
1037 dev_err(pf->dev,
1045 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0));
1046 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0));
1052 req = otx2_mbox_alloc_msg_ready(&pf->mbox);
1054 otx2_disable_mbox_intr(pf);
1057 err = otx2_sync_mbox_msg(&pf->mbox);
1059 dev_warn(pf->dev,
1061 otx2_disable_mbox_intr(pf);
1068 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf)
1070 struct mbox *mbox = &pf->mbox;
1072 if (pf->mbox_wq) {
1073 destroy_workqueue(pf->mbox_wq);
1074 pf->mbox_wq = NULL;
1084 static int otx2_pfaf_mbox_init(struct otx2_nic *pf)
1086 struct mbox *mbox = &pf->mbox;
1090 mbox->pfvf = pf;
1091 pf->mbox_wq = alloc_ordered_workqueue("otx2_pfaf_mailbox",
1093 if (!pf->mbox_wq)
1100 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM),
1103 dev_err(pf->dev, "Unable to map PFAF mailbox region\n");
1108 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base,
1113 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base,
1118 err = otx2_mbox_bbuf_init(mbox, pf->pdev);
1128 otx2_pfaf_mbox_destroy(pf);
1132 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable)
1137 mutex_lock(&pf->mbox.lock);
1139 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox);
1141 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox);
1144 mutex_unlock(&pf->mbox.lock);
1148 err = otx2_sync_mbox_msg(&pf->mbox);
1149 mutex_unlock(&pf->mbox.lock);
1153 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable)
1158 if (enable && !bitmap_empty(pf->flow_cfg->dmacflt_bmap,
1159 pf->flow_cfg->dmacflt_max_flows))
1160 netdev_warn(pf->netdev,
1163 mutex_lock(&pf->mbox.lock);
1165 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox);
1167 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox);
1170 mutex_unlock(&pf->mbox.lock);
1174 err = otx2_sync_mbox_msg(&pf->mbox);
1175 mutex_unlock(&pf->mbox.lock);
1255 struct otx2_nic *pf = data;
1261 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) {
1262 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT);
1265 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) |
1271 netdev_err(pf->netdev,
1273 qidx, otx2_read64(pf, NIX_LF_ERR_INT));
1276 netdev_err(pf->netdev, "CQ%lld: Doorbell error",
1279 netdev_err(pf->netdev,
1284 schedule_work(&pf->reset_task);
1288 for (qidx = 0; qidx < otx2_get_total_tx_queues(pf); qidx++) {
1292 sq = &pf->qset.sq[qidx];
1301 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT);
1303 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) |
1307 netdev_err(pf->netdev,
1309 qidx, otx2_read64(pf, NIX_LF_ERR_INT));
1313 sq_op_err_dbg = otx2_read64(pf, NIX_LF_SQ_OP_ERR_DBG);
1318 netdev_err(pf->netdev,
1324 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, BIT_ULL(44));
1334 mnq_err_dbg = otx2_read64(pf, NIX_LF_MNQ_ERR_DBG);
1339 netdev_err(pf->netdev,
1343 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, BIT_ULL(44));
1346 snd_err_dbg = otx2_read64(pf, NIX_LF_SEND_ERR_DBG);
1349 netdev_err(pf->netdev,
1354 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, BIT_ULL(44));
1360 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed",
1363 schedule_work(&pf->reset_task);
1372 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev;
1380 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0));
1383 pf->napi_events++;
1389 static void otx2_disable_napi(struct otx2_nic *pf)
1391 struct otx2_qset *qset = &pf->qset;
1395 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1403 static void otx2_free_cq_res(struct otx2_nic *pf)
1405 struct otx2_qset *qset = &pf->qset;
1410 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false);
1413 qmem_free(pf->dev, cq->cqe);
1417 static void otx2_free_sq_res(struct otx2_nic *pf)
1419 struct otx2_qset *qset = &pf->qset;
1424 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false);
1426 otx2_sq_free_sqbs(pf);
1427 for (qidx = 0; qidx < otx2_get_total_tx_queues(pf); qidx++) {
1432 qmem_free(pf->dev, sq->sqe);
1433 qmem_free(pf->dev, sq->tso_hdrs);
1439 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu)
1445 if (pf->hw.rbuf_len)
1446 return ALIGN(pf->hw.rbuf_len, OTX2_ALIGN) + OTX2_HEAD_ROOM;
1467 static int otx2_init_hw_resources(struct otx2_nic *pf)
1470 struct mbox *mbox = &pf->mbox;
1471 struct otx2_hw *hw = &pf->hw;
1480 hw->sqpool_cnt = otx2_get_total_tx_queues(pf);
1484 pf->tx_max_pktlen = pf->netdev->max_mtu + OTX2_ETH_HLEN;
1486 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu);
1490 err = otx2_config_npa(pf);
1495 err = otx2_config_nix(pf);
1500 if (!is_otx2_lbkvf(pf->pdev))
1501 otx2_nix_config_bp(pf, true);
1504 err = otx2_rq_aura_pool_init(pf);
1510 err = otx2_sq_aura_pool_init(pf);
1516 err = otx2_txsch_alloc(pf);
1523 if (pf->pfc_en) {
1524 err = otx2_pfc_txschq_alloc(pf);
1532 err = otx2_config_nix_queues(pf);
1539 err = otx2_txschq_config(pf, lvl, 0, false);
1547 if (pf->pfc_en) {
1548 err = otx2_pfc_txschq_config(pf);
1560 otx2_free_sq_res(pf);
1561 otx2_free_cq_res(pf);
1564 otx2_txschq_stop(pf);
1566 otx2_sq_free_sqbs(pf);
1568 otx2_free_aura_ptr(pf, AURA_NIX_RQ);
1571 otx2_aura_pool_free(pf);
1578 dev_err(pf->dev, "%s failed to free nixlf\n", __func__);
1585 dev_err(pf->dev, "%s failed to free npalf\n", __func__);
1592 static void otx2_free_hw_resources(struct otx2_nic *pf)
1594 struct otx2_qset *qset = &pf->qset;
1596 struct mbox *mbox = &pf->mbox;
1604 otx2_sqb_flush(pf);
1607 otx2_txschq_stop(pf);
1610 if (pf->pfc_en)
1611 otx2_pfc_txschq_stop(pf);
1614 otx2_clean_qos_queues(pf);
1618 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK))
1619 otx2_nix_config_bp(pf, false);
1629 otx2_cleanup_rx_cqes(pf, cq, qidx);
1631 otx2_cleanup_tx_cqes(pf, cq);
1633 otx2_free_pending_sqe(pf);
1635 otx2_free_sq_res(pf);
1638 otx2_free_aura_ptr(pf, AURA_NIX_RQ);
1640 for (qidx = 0; qidx < pf->hw.rx_queues; qidx++) {
1641 pool_id = otx2_get_pool_idx(pf, AURA_NIX_RQ, qidx);
1642 pool = &pf->qset.pool[pool_id];
1647 otx2_free_cq_res(pf);
1650 cn10k_free_all_ipolicers(pf);
1657 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN))
1660 dev_err(pf->dev, "%s failed to free nixlf\n", __func__);
1667 otx2_aura_pool_free(pf);
1674 dev_err(pf->dev, "%s failed to free npalf\n", __func__);
1694 static void otx2_do_set_rx_mode(struct otx2_nic *pf)
1696 struct net_device *netdev = pf->netdev;
1712 mutex_lock(&pf->mbox.lock);
1713 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox);
1715 mutex_unlock(&pf->mbox.lock);
1726 if (otx2_promisc_use_mce_list(pf))
1729 otx2_sync_mbox_msg(&pf->mbox);
1730 mutex_unlock(&pf->mbox.lock);
1762 struct otx2_nic *pf = netdev_priv(netdev);
1764 struct otx2_qset *qset = &pf->qset;
1773 pf->hw.non_qos_queues = pf->hw.tx_queues + pf->hw.xdp_queues;
1774 pf->hw.cint_cnt = max3(pf->hw.rx_queues, pf->hw.tx_queues,
1775 pf->hw.tc_tx_queues);
1777 pf->qset.cq_cnt = pf->hw.rx_queues + otx2_get_total_tx_queues(pf);
1779 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL);
1789 qset->cq = kcalloc(pf->qset.cq_cnt,
1794 qset->sq = kcalloc(otx2_get_total_tx_queues(pf),
1799 qset->rq = kcalloc(pf->hw.rx_queues,
1804 err = otx2_init_hw_resources(pf);
1809 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1818 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ;
1819 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ?
1820 qidx + pf->hw.rx_queues : CINT_INVALID_CQ;
1821 if (pf->xdp_prog)
1822 cq_poll->cq_ids[CQ_XDP] = (qidx < pf->hw.xdp_queues) ?
1823 (qidx + pf->hw.rx_queues +
1824 pf->hw.tx_queues) :
1829 cq_poll->cq_ids[CQ_QOS] = (qidx < pf->hw.tc_tx_queues) ?
1830 (qidx + pf->hw.rx_queues +
1831 pf->hw.non_qos_queues) :
1834 cq_poll->dev = (void *)pf;
1842 err = otx2_hw_set_mtu(pf, netdev->mtu);
1847 otx2_setup_segmentation(pf);
1850 err = otx2_rss_init(pf);
1855 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START;
1856 irq_name = &pf->hw.irq_name[vec * NAME_SIZE];
1858 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name);
1860 err = request_irq(pci_irq_vector(pf->pdev, vec),
1861 otx2_q_intr_handler, 0, irq_name, pf);
1863 dev_err(pf->dev,
1865 rvu_get_pf(pf->pcifunc));
1870 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0));
1873 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START;
1874 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1875 irq_name = &pf->hw.irq_name[vec * NAME_SIZE];
1877 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name,
1880 err = request_irq(pci_irq_vector(pf->pdev, vec),
1884 dev_err(pf->dev,
1886 rvu_get_pf(pf->pcifunc), qidx);
1891 otx2_config_irq_coalescing(pf, qidx);
1894 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0));
1895 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0));
1898 otx2_set_cints_affinity(pf);
1900 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT)
1901 otx2_enable_rxvlan(pf, true);
1904 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) {
1905 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED;
1906 otx2_config_hw_tx_tstamp(pf, true);
1908 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) {
1909 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED;
1910 otx2_config_hw_rx_tstamp(pf, true);
1913 pf->flags &= ~OTX2_FLAG_INTF_DOWN;
1918 otx2_qos_config_txschq(pf);
1921 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK))
1922 otx2_handle_link_event(pf);
1925 if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT)
1926 otx2_dmacflt_reinstall_flows(pf);
1928 otx2_tc_apply_ingress_police_rules(pf);
1930 err = otx2_rxtx_enable(pf, true);
1941 otx2_do_set_rx_mode(pf);
1946 otx2_rxtx_enable(pf, false);
1950 pf->flags |= OTX2_FLAG_INTF_DOWN;
1952 otx2_free_cints(pf, qidx);
1953 vec = pci_irq_vector(pf->pdev,
1954 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START);
1955 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0));
1956 free_irq(vec, pf);
1958 otx2_disable_napi(pf);
1959 otx2_free_hw_resources(pf);
1971 struct otx2_nic *pf = netdev_priv(netdev);
1973 struct otx2_qset *qset = &pf->qset;
1978 if (pf->flags & OTX2_FLAG_INTF_DOWN)
1984 pf->flags |= OTX2_FLAG_INTF_DOWN;
1989 otx2_rxtx_enable(pf, false);
1992 rss = &pf->hw.rss_info;
1998 vec = pci_irq_vector(pf->pdev,
1999 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START);
2000 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0));
2001 free_irq(vec, pf);
2004 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START;
2005 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
2007 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0));
2009 synchronize_irq(pci_irq_vector(pf->pdev, vec));
2018 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++)
2019 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work);
2020 devm_kfree(pf->dev, pf->refill_wrk);
2022 otx2_free_hw_resources(pf);
2023 otx2_free_cints(pf, pf->hw.cint_cnt);
2024 otx2_disable_napi(pf);
2042 struct otx2_nic *pf = netdev_priv(netdev);
2051 sq_idx = (qidx >= pf->hw.tx_queues) ? (qidx + pf->hw.xdp_queues) : qidx;
2055 (!skb_shinfo(skb)->gso_size && skb->len > pf->tx_max_pktlen)) {
2060 sq = &pf->qset.sq[sq_idx];
2078 static int otx2_qos_select_htb_queue(struct otx2_nic *pf, struct sk_buff *skb,
2086 classid = READ_ONCE(pf->qos.defcls);
2091 return otx2_get_txq_by_classid(pf, classid);
2097 struct otx2_nic *pf = netdev_priv(netdev);
2104 qos_enabled = netdev->real_num_tx_queues > pf->hw.tx_queues;
2109 u16 htb_maj_id = smp_load_acquire(&pf->qos.maj_id);
2112 txq = otx2_qos_select_htb_queue(pf, skb, htb_maj_id);
2125 if ((vlan_prio > pf->hw.tx_queues - 1) ||
2126 !pf->pfc_alloc_status[vlan_prio])
2135 return txq % pf->hw.tx_queues;
2154 struct otx2_nic *pf = netdev_priv(netdev);
2156 queue_work(pf->otx2_wq, &pf->rx_mode_work);
2161 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work);
2163 otx2_do_set_rx_mode(pf);
2170 struct otx2_nic *pf = netdev_priv(netdev);
2173 return otx2_cgx_config_loopback(pf,
2177 return otx2_enable_rxvlan(pf,
2185 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task);
2187 if (!netif_running(pf->netdev))
2191 otx2_stop(pf->netdev);
2192 pf->reset_count++;
2193 otx2_open(pf->netdev);
2194 netif_trans_update(pf->netdev);
2344 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac)
2349 mutex_lock(&pf->mbox.lock);
2350 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox);
2359 req->channel = pf->hw.rx_chan_base;
2366 err = otx2_sync_mbox_msg(&pf->mbox);
2368 mutex_unlock(&pf->mbox.lock);
2374 struct otx2_nic *pf = netdev_priv(netdev);
2375 struct pci_dev *pdev = pf->pdev;
2382 if (vf >= pf->total_vfs)
2388 config = &pf->vf_configs[vf];
2391 ret = otx2_do_set_vf_mac(pf, vf, mac);
2399 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos,
2402 struct otx2_flow_config *flow_cfg = pf->flow_cfg;
2411 config = &pf->vf_configs[vf];
2416 mutex_lock(&pf->mbox.lock);
2420 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox);
2429 err = otx2_sync_mbox_msg(&pf->mbox);
2436 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox);
2444 err = otx2_sync_mbox_msg(&pf->mbox);
2449 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox);
2457 err = otx2_sync_mbox_msg(&pf->mbox);
2463 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox);
2476 req->channel = pf->hw.rx_chan_base;
2484 err = otx2_sync_mbox_msg(&pf->mbox);
2489 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox);
2501 err = otx2_sync_mbox_msg(&pf->mbox);
2506 (&pf->mbox.mbox, 0, &vtag_req->hdr);
2513 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox);
2523 req->channel = pf->hw.tx_chan_base;
2531 err = otx2_sync_mbox_msg(&pf->mbox);
2534 mutex_unlock(&pf->mbox.lock);
2541 struct otx2_nic *pf = netdev_priv(netdev);
2542 struct pci_dev *pdev = pf->pdev;
2557 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT))
2560 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto);
2566 struct otx2_nic *pf = netdev_priv(netdev);
2567 struct pci_dev *pdev = pf->pdev;
2576 config = &pf->vf_configs[vf];
2585 static int otx2_xdp_xmit_tx(struct otx2_nic *pf, struct xdp_frame *xdpf,
2592 dma_addr = otx2_dma_map_page(pf, virt_to_page(xdpf->data),
2595 if (dma_mapping_error(pf->dev, dma_addr))
2598 err = otx2_xdp_sq_append_pkt(pf, dma_addr, xdpf->len, qidx);
2600 otx2_dma_unmap_page(pf, dma_addr, xdpf->len, DMA_TO_DEVICE);
2611 struct otx2_nic *pf = netdev_priv(netdev);
2619 qidx += pf->hw.tx_queues;
2620 sq = pf->xdp_prog ? &pf->qset.sq[qidx] : NULL;
2633 err = otx2_xdp_xmit_tx(pf, xdpf, qidx);
2640 static int otx2_xdp_setup(struct otx2_nic *pf, struct bpf_prog *prog)
2642 struct net_device *dev = pf->netdev;
2643 bool if_up = netif_running(pf->netdev);
2652 otx2_stop(pf->netdev);
2654 old_prog = xchg(&pf->xdp_prog, prog);
2659 if (pf->xdp_prog)
2660 bpf_prog_add(pf->xdp_prog, pf->hw.rx_queues - 1);
2665 if (pf->xdp_prog) {
2666 pf->hw.xdp_queues = pf->hw.rx_queues;
2669 pf->hw.xdp_queues = 0;
2674 otx2_open(pf->netdev);
2681 struct otx2_nic *pf = netdev_priv(netdev);
2685 return otx2_xdp_setup(pf, xdp->prog);
2691 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf,
2697 mutex_lock(&pf->mbox.lock);
2698 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox);
2708 if (pf->vf_configs[vf].trusted)
2713 rc = otx2_sync_mbox_msg(&pf->mbox);
2715 mutex_unlock(&pf->mbox.lock);
2722 struct otx2_nic *pf = netdev_priv(netdev);
2723 struct pci_dev *pdev = pf->pdev;
2729 if (pf->vf_configs[vf].trusted == enable)
2732 pf->vf_configs[vf].trusted = enable;
2733 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF);
2736 pf->vf_configs[vf].trusted = !enable;
2738 netdev_info(pf->netdev, "VF %d is %strusted\n",
2768 static int otx2_wq_init(struct otx2_nic *pf)
2770 pf->otx2_wq = create_singlethread_workqueue("otx2_wq");
2771 if (!pf->otx2_wq)
2774 INIT_WORK(&pf->rx_mode_work, otx2_rx_mode_wrk_handler);
2775 INIT_WORK(&pf->reset_task, otx2_reset_task);
2797 static int otx2_realloc_msix_vectors(struct otx2_nic *pf)
2799 struct otx2_hw *hw = &pf->hw;
2808 otx2_disable_mbox_intr(pf);
2812 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n",
2817 return otx2_register_mbox_intr(pf, false);
2820 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf)
2824 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs,
2827 if (!pf->vf_configs)
2830 for (i = 0; i < pf->total_vfs; i++) {
2831 pf->vf_configs[i].pf = pf;
2832 pf->vf_configs[i].intf_down = true;
2833 pf->vf_configs[i].trusted = false;
2834 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work,
2841 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf)
2845 if (!pf->vf_configs)
2848 for (i = 0; i < pf->total_vfs; i++) {
2849 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work);
2850 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM);
2859 struct otx2_nic *pf;
2887 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount + qos_txqs, qcount);
2895 pf = netdev_priv(netdev);
2896 pf->netdev = netdev;
2897 pf->pdev = pdev;
2898 pf->dev = dev;
2899 pf->total_vfs = pci_sriov_get_totalvfs(pdev);
2900 pf->flags |= OTX2_FLAG_INTF_DOWN;
2902 hw = &pf->hw;
2928 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
2929 if (!pf->reg_base) {
2935 err = otx2_check_pf_usable(pf);
2947 otx2_setup_dev_hw_settings(pf);
2950 err = otx2_pfaf_mbox_init(pf);
2955 err = otx2_register_mbox_intr(pf, true);
2962 err = otx2_attach_npa_nix(pf);
2966 err = otx2_realloc_msix_vectors(pf);
2974 err = cn10k_lmtst_init(pf);
2982 otx2_ptp_init(pf);
2995 pf->iommu_domain = iommu_get_domain_for_dev(dev);
3003 err = otx2_mcam_flow_init(pf);
3007 err = cn10k_mcs_init(pf);
3011 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT)
3014 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT)
3021 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT)
3027 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT)
3039 netdev->max_mtu = otx2_get_max_mtu(pf);
3047 err = otx2_wq_init(pf);
3053 err = otx2_init_tc(pf);
3057 err = otx2_register_dl(pf);
3062 err = otx2_sriov_vfcfg_init(pf);
3067 otx2_cgx_config_linkevents(pf, true);
3075 otx2_qos_init(pf, qos_txqs);
3080 otx2_shutdown_tc(pf);
3082 otx2_mcam_flow_del(pf);
3086 cn10k_mcs_free(pf);
3088 otx2_mcam_flow_del(pf);
3090 otx2_ptp_destroy(pf);
3092 if (pf->hw.lmt_info)
3093 free_percpu(pf->hw.lmt_info);
3094 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag))
3095 qmem_free(pf->dev, pf->dync_lmt);
3096 otx2_detach_resources(&pf->mbox);
3098 otx2_disable_mbox_intr(pf);
3100 otx2_pfaf_mbox_destroy(pf);
3117 struct otx2_nic *pf;
3122 vf_idx = config - config->pf->vf_configs;
3123 pf = config->pf;
3128 mutex_lock(&pf->mbox.lock);
3132 if (!otx2_mbox_wait_for_zero(&pf->mbox_pfvf[0].mbox_up, vf_idx)) {
3134 mutex_unlock(&pf->mbox.lock);
3138 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx,
3141 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx);
3142 mutex_unlock(&pf->mbox.lock);
3149 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info));
3151 otx2_mbox_wait_for_zero(&pf->mbox_pfvf[0].mbox_up, vf_idx);
3153 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx);
3155 mutex_unlock(&pf->mbox.lock);
3161 struct otx2_nic *pf = netdev_priv(netdev);
3165 ret = otx2_pfvf_mbox_init(pf, numvfs);
3169 ret = otx2_register_pfvf_mbox_intr(pf, numvfs);
3173 ret = otx2_pf_flr_init(pf, numvfs);
3177 ret = otx2_register_flr_me_intr(pf, numvfs);
3187 otx2_disable_flr_me_intr(pf);
3189 otx2_flr_wq_destroy(pf);
3191 otx2_disable_pfvf_mbox_intr(pf, numvfs);
3193 otx2_pfvf_mbox_destroy(pf);
3200 struct otx2_nic *pf = netdev_priv(netdev);
3208 otx2_disable_flr_me_intr(pf);
3209 otx2_flr_wq_destroy(pf);
3210 otx2_disable_pfvf_mbox_intr(pf, numvfs);
3211 otx2_pfvf_mbox_destroy(pf);
3227 struct otx2_nic *pf;
3232 pf = netdev_priv(netdev);
3234 pf->flags |= OTX2_FLAG_PF_SHUTDOWN;
3236 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED)
3237 otx2_config_hw_tx_tstamp(pf, false);
3238 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED)
3239 otx2_config_hw_rx_tstamp(pf, false);
3242 if (pf->flags & OTX2_FLAG_RX_PAUSE_ENABLED ||
3243 (pf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) {
3244 pf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED;
3245 pf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED;
3246 otx2_config_pause_frm(pf);
3251 if (pf->pfc_en) {
3252 pf->pfc_en = 0;
3253 otx2_config_priority_flow_ctrl(pf);
3256 cancel_work_sync(&pf->reset_task);
3258 otx2_cgx_config_linkevents(pf, false);
3260 otx2_unregister_dl(pf);
3262 cn10k_mcs_free(pf);
3263 otx2_sriov_disable(pf->pdev);
3264 otx2_sriov_vfcfg_cleanup(pf);
3265 if (pf->otx2_wq)
3266 destroy_workqueue(pf->otx2_wq);
3268 otx2_ptp_destroy(pf);
3269 otx2_mcam_flow_del(pf);
3270 otx2_shutdown_tc(pf);
3271 otx2_shutdown_qos(pf);
3272 otx2_detach_resources(&pf->mbox);
3273 if (pf->hw.lmt_info)
3274 free_percpu(pf->hw.lmt_info);
3275 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag))
3276 qmem_free(pf->dev, pf->dync_lmt);
3277 otx2_disable_mbox_intr(pf);
3278 otx2_pfaf_mbox_destroy(pf);
3279 pci_free_irq_vectors(pf->pdev);