Lines Matching refs:pfvf
20 struct otx2_nic *pfvf, int qidx)
25 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS);
28 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS);
33 struct otx2_nic *pfvf, int qidx)
38 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS);
41 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS);
45 void otx2_update_lmac_stats(struct otx2_nic *pfvf)
49 if (!netif_running(pfvf->netdev))
52 mutex_lock(&pfvf->mbox.lock);
53 req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox);
55 mutex_unlock(&pfvf->mbox.lock);
59 otx2_sync_mbox_msg(&pfvf->mbox);
60 mutex_unlock(&pfvf->mbox.lock);
63 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf)
67 if (!netif_running(pfvf->netdev))
69 mutex_lock(&pfvf->mbox.lock);
70 req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox);
72 otx2_sync_mbox_msg(&pfvf->mbox);
73 mutex_unlock(&pfvf->mbox.lock);
76 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx)
78 struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx];
80 if (!pfvf->qset.rq)
83 otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx);
87 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx)
89 struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx];
91 if (!pfvf->qset.sq)
94 if (qidx >= pfvf->hw.non_qos_queues) {
95 if (!test_bit(qidx - pfvf->hw.non_qos_queues, pfvf->qos.qos_sq_bmap))
99 otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx);
103 void otx2_get_dev_stats(struct otx2_nic *pfvf)
105 struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats;
129 struct otx2_nic *pfvf = netdev_priv(netdev);
132 otx2_get_dev_stats(pfvf);
134 dev_stats = &pfvf->hw.dev_stats;
147 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac)
152 mutex_lock(&pfvf->mbox.lock);
153 req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox);
155 mutex_unlock(&pfvf->mbox.lock);
161 err = otx2_sync_mbox_msg(&pfvf->mbox);
162 mutex_unlock(&pfvf->mbox.lock);
166 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf,
174 mutex_lock(&pfvf->mbox.lock);
175 req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox);
177 mutex_unlock(&pfvf->mbox.lock);
181 err = otx2_sync_mbox_msg(&pfvf->mbox);
183 mutex_unlock(&pfvf->mbox.lock);
187 msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
189 mutex_unlock(&pfvf->mbox.lock);
194 mutex_unlock(&pfvf->mbox.lock);
201 struct otx2_nic *pfvf = netdev_priv(netdev);
207 if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) {
211 pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT)
212 otx2_install_rxvlan_offload_flow(pfvf);
214 if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT)
215 otx2_dmacflt_update_pfmac_flow(pfvf);
224 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu)
230 maxlen = otx2_get_max_mtu(pfvf) + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN;
232 mutex_lock(&pfvf->mbox.lock);
233 req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox);
235 mutex_unlock(&pfvf->mbox.lock);
239 req->maxlen = pfvf->netdev->mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN;
242 if (is_otx2_lbkvf(pfvf->pdev))
245 err = otx2_sync_mbox_msg(&pfvf->mbox);
246 mutex_unlock(&pfvf->mbox.lock);
250 int otx2_config_pause_frm(struct otx2_nic *pfvf)
255 if (is_otx2_lbkvf(pfvf->pdev))
258 mutex_lock(&pfvf->mbox.lock);
259 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox);
265 req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED);
266 req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED);
269 err = otx2_sync_mbox_msg(&pfvf->mbox);
271 mutex_unlock(&pfvf->mbox.lock);
276 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf)
278 struct otx2_rss_info *rss = &pfvf->hw.rss_info;
283 mutex_lock(&pfvf->mbox.lock);
284 req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox);
286 mutex_unlock(&pfvf->mbox.lock);
293 err = otx2_sync_mbox_msg(&pfvf->mbox);
298 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
304 pfvf->hw.flowkey_alg_idx = rsp->alg_idx;
306 mutex_unlock(&pfvf->mbox.lock);
310 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id)
312 struct otx2_rss_info *rss = &pfvf->hw.rss_info;
314 struct mbox *mbox = &pfvf->mbox;
352 void otx2_set_rss_key(struct otx2_nic *pfvf)
354 struct otx2_rss_info *rss = &pfvf->hw.rss_info;
366 otx2_write64(pfvf, NIX_LF_RX_SECRETX(5),
371 otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++);
375 int otx2_rss_init(struct otx2_nic *pfvf)
377 struct otx2_rss_info *rss = &pfvf->hw.rss_info;
386 otx2_set_rss_key(pfvf);
388 if (!netif_is_rxfh_configured(pfvf->netdev)) {
399 pfvf->hw.rx_queues);
401 ret = otx2_set_rss_table(pfvf, DEFAULT_RSS_CONTEXT_GROUP);
412 ret = otx2_set_flowkey_cfg(pfvf);
454 void otx2_setup_segmentation(struct otx2_nic *pfvf)
458 struct otx2_hw *hw = &pfvf->hw;
461 mutex_lock(&pfvf->mbox.lock);
464 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox);
471 err = otx2_sync_mbox_msg(&pfvf->mbox);
476 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr);
483 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox);
490 err = otx2_sync_mbox_msg(&pfvf->mbox);
495 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr);
500 mutex_unlock(&pfvf->mbox.lock);
503 mutex_unlock(&pfvf->mbox.lock);
504 netdev_info(pfvf->netdev,
506 pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4;
509 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx)
517 otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx),
518 ((u64)(pfvf->hw.cq_time_wait * 10) << 48) |
519 ((u64)pfvf->hw.cq_qcount_wait << 32) |
520 (pfvf->hw.cq_ecount_wait - 1));
523 static int otx2_alloc_pool_buf(struct otx2_nic *pfvf, struct otx2_pool *pool,
541 static int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
547 return otx2_alloc_pool_buf(pfvf, pool, dma);
553 *dma = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize,
555 if (unlikely(dma_mapping_error(pfvf->dev, *dma))) {
563 int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
569 ret = __otx2_alloc_rbuf(pfvf, pool, dma);
574 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq,
577 if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma)))
584 struct otx2_nic *pfvf = netdev_priv(netdev);
586 schedule_work(&pfvf->reset_task);
592 struct otx2_nic *pfvf = netdev_priv(netdev);
595 err = otx2_hw_get_mac_addr(pfvf, netdev);
597 dev_warn(pfvf->dev, "Failed to read mac from hardware\n");
605 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool txschq_for_pfc)
608 struct otx2_hw *hw = &pfvf->hw;
613 dwrr_val = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen);
615 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox);
625 schq_list = pfvf->pfc_schq_list;
632 req->regval[0] = ((u64)pfvf->tx_max_pktlen << 8) | OTX2_MIN_MTU;
636 if (!is_dev_otx2(pfvf->pdev))
708 return otx2_sync_mbox_msg(&pfvf->mbox);
712 int otx2_smq_flush(struct otx2_nic *pfvf, int smq)
717 mutex_lock(&pfvf->mbox.lock);
719 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox);
721 mutex_unlock(&pfvf->mbox.lock);
730 rc = otx2_sync_mbox_msg(&pfvf->mbox);
731 mutex_unlock(&pfvf->mbox.lock);
736 int otx2_txsch_alloc(struct otx2_nic *pfvf)
743 req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox);
750 rc = otx2_sync_mbox_msg(&pfvf->mbox);
755 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
762 pfvf->hw.txschq_list[lvl][schq] =
765 pfvf->hw.txschq_link_cfg_lvl = rsp->link_cfg_lvl;
766 pfvf->hw.txschq_aggr_lvl_rr_prio = rsp->aggr_lvl_rr_prio;
771 void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq)
776 mutex_lock(&pfvf->mbox.lock);
778 free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox);
780 mutex_unlock(&pfvf->mbox.lock);
781 netdev_err(pfvf->netdev,
789 err = otx2_sync_mbox_msg(&pfvf->mbox);
791 netdev_err(pfvf->netdev,
795 mutex_unlock(&pfvf->mbox.lock);
799 void otx2_txschq_stop(struct otx2_nic *pfvf)
805 otx2_txschq_free_one(pfvf, lvl,
806 pfvf->hw.txschq_list[lvl][0]);
811 pfvf->hw.txschq_list[lvl][schq] = 0;
816 void otx2_sqb_flush(struct otx2_nic *pfvf)
822 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS);
823 for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) {
824 sq = &pfvf->qset.sq[qidx];
853 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura)
855 struct otx2_qset *qset = &pfvf->qset;
859 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
867 aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1;
873 aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
874 aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
883 return otx2_sync_mbox_msg(&pfvf->mbox);
888 struct otx2_nic *pfvf = dev;
892 sq = &pfvf->qset.sq[qidx];
893 sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx));
895 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
899 aq->sq.cq = pfvf->hw.rx_queues + qidx;
903 aq->sq.smq = otx2_get_smq_idx(pfvf, qidx);
904 aq->sq.smq_rr_quantum = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen);
905 aq->sq.default_chan = pfvf->hw.tx_chan_base;
913 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt));
920 return otx2_sync_mbox_msg(&pfvf->mbox);
923 int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura)
925 struct otx2_qset *qset = &pfvf->qset;
930 pool = &pfvf->qset.pool[sqb_aura];
935 err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size);
939 if (qidx < pfvf->hw.tx_queues) {
940 err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt,
951 if (pfvf->ptp && qidx < pfvf->hw.tx_queues) {
952 err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt,
963 sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1;
969 sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0));
974 err = pfvf->hw_ops->sq_aq_init(pfvf, qidx, sqb_aura);
985 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx)
987 struct otx2_qset *qset = &pfvf->qset;
994 non_xdp_queues = pfvf->hw.rx_queues + pfvf->hw.tx_queues;
995 if (qidx < pfvf->hw.rx_queues) {
999 if (pfvf->xdp_prog)
1000 xdp_rxq_info_reg(&cq->xdp_rxq, pfvf->netdev, qidx, 0);
1003 cq->cint_idx = qidx - pfvf->hw.rx_queues;
1006 if (pfvf->hw.xdp_queues &&
1007 qidx < non_xdp_queues + pfvf->hw.xdp_queues) {
1014 pfvf->hw.xdp_queues;
1018 cq->cqe_size = pfvf->qset.xqe_size;
1021 err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size);
1031 (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx;
1036 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
1049 if (qidx < pfvf->hw.rx_queues) {
1050 aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt);
1053 if (!is_otx2_lbkvf(pfvf->pdev)) {
1057 aq->cq.bpid = pfvf->bpid[pfvf->queue_to_pfc_map[qidx]];
1059 aq->cq.bpid = pfvf->bpid[0];
1063 aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
1072 return otx2_sync_mbox_msg(&pfvf->mbox);
1079 struct otx2_nic *pfvf;
1083 pfvf = wrk->pf;
1084 qidx = wrk - pfvf->refill_wrk;
1085 cq = &pfvf->qset.cq[qidx];
1094 int otx2_config_nix_queues(struct otx2_nic *pfvf)
1099 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) {
1100 u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx);
1102 err = otx2_rq_init(pfvf, qidx, lpb_aura);
1108 for (qidx = 0; qidx < pfvf->hw.non_qos_queues; qidx++) {
1109 u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1111 err = otx2_sq_init(pfvf, qidx, sqb_aura);
1117 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) {
1118 err = otx2_cq_init(pfvf, qidx);
1123 pfvf->cq_op_addr = (__force u64 *)otx2_get_regaddr(pfvf,
1127 pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt,
1129 if (!pfvf->refill_wrk)
1132 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) {
1133 pfvf->refill_wrk[qidx].pf = pfvf;
1134 INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work,
1140 int otx2_config_nix(struct otx2_nic *pfvf)
1146 pfvf->qset.xqe_size = pfvf->hw.xqe_size;
1149 nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox);
1154 nixlf->rq_cnt = pfvf->hw.rx_queues;
1155 nixlf->sq_cnt = otx2_get_total_tx_queues(pfvf);
1156 nixlf->cq_cnt = pfvf->qset.cq_cnt;
1159 nixlf->xqe_sz = pfvf->hw.xqe_size == 128 ? NIX_XQESZ_W16 : NIX_XQESZ_W64;
1170 err = otx2_sync_mbox_msg(&pfvf->mbox);
1174 rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0,
1185 void otx2_sq_free_sqbs(struct otx2_nic *pfvf)
1187 struct otx2_qset *qset = &pfvf->qset;
1188 struct otx2_hw *hw = &pfvf->hw;
1193 for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) {
1201 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1202 dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size,
1211 void otx2_free_bufs(struct otx2_nic *pfvf, struct otx2_pool *pool,
1217 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1223 dma_unmap_page_attrs(pfvf->dev, iova, size,
1231 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type)
1238 pool_start = otx2_get_pool_idx(pfvf, type, 0);
1239 pool_end = pool_start + pfvf->hw.sqpool_cnt;
1240 size = pfvf->hw.sqb_size;
1243 pool_start = otx2_get_pool_idx(pfvf, type, 0);
1244 pool_end = pfvf->hw.rqpool_cnt;
1245 size = pfvf->rbsize;
1250 iova = otx2_aura_allocptr(pfvf, pool_id);
1251 pool = &pfvf->qset.pool[pool_id];
1256 otx2_free_bufs(pfvf, pool, iova, size);
1258 iova = otx2_aura_allocptr(pfvf, pool_id);
1263 void otx2_aura_pool_free(struct otx2_nic *pfvf)
1268 if (!pfvf->qset.pool)
1271 for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) {
1272 pool = &pfvf->qset.pool[pool_id];
1273 qmem_free(pfvf->dev, pool->stack);
1274 qmem_free(pfvf->dev, pool->fc_addr);
1278 devm_kfree(pfvf->dev, pfvf->qset.pool);
1279 pfvf->qset.pool = NULL;
1282 int otx2_aura_init(struct otx2_nic *pfvf, int aura_id,
1289 pool = &pfvf->qset.pool[pool_id];
1295 err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN);
1301 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1304 err = otx2_sync_mbox_msg(&pfvf->mbox);
1307 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1326 if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) {
1340 if (pfvf->nix_blkaddr == BLKADDR_NIX1)
1343 aq->aura.nix0_bpid = pfvf->bpid[pfvf->queue_to_pfc_map[aura_id]];
1345 aq->aura.nix0_bpid = pfvf->bpid[0];
1359 int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id,
1367 pool = &pfvf->qset.pool[pool_id];
1369 err = qmem_alloc(pfvf->dev, &pool->stack,
1370 stack_pages, pfvf->hw.stack_pg_bytes);
1377 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1380 err = otx2_sync_mbox_msg(&pfvf->mbox);
1382 qmem_free(pfvf->dev, pool->stack);
1385 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1387 qmem_free(pfvf->dev, pool->stack);
1415 pp_params.dev = pfvf->dev;
1419 netdev_err(pfvf->netdev, "Creation of page pool failed\n");
1426 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf)
1429 struct otx2_qset *qset = &pfvf->qset;
1430 struct otx2_hw *hw = &pfvf->hw;
1449 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1451 err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs);
1456 err = otx2_pool_init(pfvf, pool_id, stack_pages,
1463 err = otx2_sync_mbox_msg(&pfvf->mbox);
1469 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1470 pool = &pfvf->qset.pool[pool_id];
1481 err = otx2_alloc_rbuf(pfvf, pool, &bufptr);
1484 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr);
1493 otx2_mbox_reset(&pfvf->mbox.mbox, 0);
1494 otx2_aura_pool_free(pfvf);
1498 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf)
1500 struct otx2_hw *hw = &pfvf->hw;
1506 num_ptrs = pfvf->qset.rqe_cnt;
1512 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq);
1514 err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs);
1519 err = otx2_pool_init(pfvf, pool_id, stack_pages,
1520 num_ptrs, pfvf->rbsize, AURA_NIX_RQ);
1526 err = otx2_sync_mbox_msg(&pfvf->mbox);
1532 pool = &pfvf->qset.pool[pool_id];
1534 err = otx2_alloc_rbuf(pfvf, pool, &bufptr);
1537 pfvf->hw_ops->aura_freeptr(pfvf, pool_id,
1543 otx2_mbox_reset(&pfvf->mbox.mbox, 0);
1544 otx2_aura_pool_free(pfvf);
1548 int otx2_config_npa(struct otx2_nic *pfvf)
1550 struct otx2_qset *qset = &pfvf->qset;
1552 struct otx2_hw *hw = &pfvf->hw;
1562 qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt,
1568 npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox);
1577 return otx2_sync_mbox_msg(&pfvf->mbox);
1601 int otx2_attach_npa_nix(struct otx2_nic *pfvf)
1607 mutex_lock(&pfvf->mbox.lock);
1609 attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox);
1611 mutex_unlock(&pfvf->mbox.lock);
1619 err = otx2_sync_mbox_msg(&pfvf->mbox);
1621 mutex_unlock(&pfvf->mbox.lock);
1625 pfvf->nix_blkaddr = BLKADDR_NIX0;
1630 if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL)
1631 pfvf->nix_blkaddr = BLKADDR_NIX1;
1634 msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox);
1636 mutex_unlock(&pfvf->mbox.lock);
1640 err = otx2_sync_mbox_msg(&pfvf->mbox);
1642 mutex_unlock(&pfvf->mbox.lock);
1645 mutex_unlock(&pfvf->mbox.lock);
1647 if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID ||
1648 pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) {
1649 dev_err(pfvf->dev,
1677 dev_err(mbox->pfvf->dev, "%s failed to disable context\n",
1683 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable)
1688 req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox);
1690 req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox);
1697 req->chan_cnt = pfvf->pfc_en ? IEEE_8021QAZ_MAX_TCS : 1;
1698 req->bpid_per_chan = pfvf->pfc_en ? 1 : 0;
1704 return otx2_sync_mbox_msg(&pfvf->mbox);
1709 void mbox_handler_cgx_stats(struct otx2_nic *pfvf,
1715 pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id];
1717 pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id];
1720 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf,
1723 pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks;
1724 pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks;
1727 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf,
1730 pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs;
1731 pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes;
1735 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf,
1738 pfvf->hw.sqb_size = rsp->sqb_size;
1739 pfvf->hw.rx_chan_base = rsp->rx_chan_base;
1740 pfvf->hw.tx_chan_base = rsp->tx_chan_base;
1741 pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx;
1742 pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx;
1743 pfvf->hw.cgx_links = rsp->cgx_links;
1744 pfvf->hw.lbk_links = rsp->lbk_links;
1745 pfvf->hw.tx_link = rsp->tx_link;
1749 void mbox_handler_msix_offset(struct otx2_nic *pfvf,
1752 pfvf->hw.npa_msixoff = rsp->npa_msixoff;
1753 pfvf->hw.nix_msixoff = rsp->nix_msixoff;
1757 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf,
1764 pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF;
1769 void otx2_free_cints(struct otx2_nic *pfvf, int n)
1771 struct otx2_qset *qset = &pfvf->qset;
1772 struct otx2_hw *hw = &pfvf->hw;
1778 int vector = pci_irq_vector(pfvf->pdev, irq);
1786 void otx2_set_cints_affinity(struct otx2_nic *pfvf)
1788 struct otx2_hw *hw = &pfvf->hw;
1795 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) {
1801 irq = pci_irq_vector(pfvf->pdev, vec);
1810 static u32 get_dwrr_mtu(struct otx2_nic *pfvf, struct nix_hw_info *hw)
1812 if (is_otx2_lbkvf(pfvf->pdev)) {
1813 pfvf->hw.smq_link_type = SMQ_LINK_TYPE_LBK;
1817 pfvf->hw.smq_link_type = SMQ_LINK_TYPE_RPM;
1821 u16 otx2_get_max_mtu(struct otx2_nic *pfvf)
1828 mutex_lock(&pfvf->mbox.lock);
1830 req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox);
1836 rc = otx2_sync_mbox_msg(&pfvf->mbox);
1839 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
1850 pfvf->hw.dwrr_mtu = get_dwrr_mtu(pfvf, rsp);
1851 if (!pfvf->hw.dwrr_mtu)
1852 pfvf->hw.dwrr_mtu = 1;
1856 mutex_unlock(&pfvf->mbox.lock);
1858 dev_warn(pfvf->dev,
1869 struct otx2_nic *pfvf = netdev_priv(netdev);
1874 otx2_destroy_ntuple_flows(pfvf);
1877 if (!pfvf->flow_cfg->max_flows) {
1885 otx2_tc_flower_rule_cnt(pfvf)) {
1891 otx2_tc_flower_rule_cnt(pfvf) && !(changed & NETIF_F_HW_TC)) {
1903 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \