octeontx2/af/rvu_npc_fs.c

73 const char *npc_get_field_name(u8 hdr)
75 	if (hdr >= ARRAY_SIZE(npc_flow_names))
78 	return npc_flow_names[hdr];
166 	input->layer_mdata.hdr = FIELD_GET(NPC_HDR_OFFSET, cfg);
464 	u8 hdr, key, nr_bytes, bit_offset;
470 	hdr = FIELD_GET(NPC_HDR_OFFSET, cfg);
489 		if ((hstart) >= hdr &&					       \
490 		    ((hstart) + (hlen)) <= (hdr + nr_bytes)) {	               \
491 			bit_offset = (hdr + nr_bytes - (hstart) - (hlen)) * 8; \
565 	int hdr;
570 	for (hdr = NPC_DMAC; hdr < NPC_HEADER_FIELDS_MAX; hdr++) {
571 		if (npc_check_field(rvu, blkaddr, hdr, intf))
572 			*features |= BIT_ULL(hdr);
623 	for (hdr = NPC_MPLS1_LBTCBOS; hdr <= NPC_MPLS4_TTL; hdr++) {
624 		if (npc_check_field(rvu, blkaddr, hdr, intf))
625 			*features |= BIT_ULL(hdr);
1090 	free_req.hdr.pcifunc = pcifunc;
1105 	cntr_req.hdr.pcifunc = pcifunc;
1135 	if (req->hdr.pcifunc &&
1137 		mce_index = rvu_nix_mcast_get_mce_index(rvu, req->hdr.pcifunc, req->index);
1222 	if (is_pffunc_af(req->hdr.pcifunc))
1267 	u16 owner = req->hdr.pcifunc;
1334 	write_req.hdr.pcifunc = owner;
1340 		write_req.hdr.pcifunc = 0;
1404 		return rvu_nix_setup_ratelimit_aggr(rvu, req->hdr.pcifunc,
1408 		return rvu_nix_mcast_update_mcam_entry(rvu, req->hdr.pcifunc,
1418 	bool from_vf = !!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK);
1442 	if (is_pffunc_af(req->hdr.pcifunc) &&
1473 	if (!req->hdr.pcifunc)
1477 		target = (req->hdr.pcifunc & ~RVU_PFVF_FUNC_MASK) | req->vf;
1483 		target = req->hdr.pcifunc;
1486 	if (!is_pffunc_af(req->hdr.pcifunc))
1496 	if (req->hdr.pcifunc && !from_vf && req->vf)
1555 	dis_req.hdr.pcifunc = pcifunc;
1570 	u16 pcifunc = req->hdr.pcifunc;
1632 	write_req.hdr.pcifunc = rule->owner;
1773 	cntr_req.hdr.pcifunc = 0; /* AF request */