octeontx2/af/rvu_npa.c

66 	int blkaddr, npalf, rc = 0;
78 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, pcifunc);
79 	if (!pfvf->npalf || blkaddr < 0)
82 	block = &hw->block[blkaddr];
337 	int blkaddr;
347 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, pcifunc);
348 	if (!pfvf->npalf || blkaddr < 0)
351 	block = &hw->block[blkaddr];
363 	ctx_cfg = rvu_read64(rvu, blkaddr, NPA_AF_CONST1);
389 	cfg = rvu_read64(rvu, blkaddr, NPA_AF_CONST);
398 	cfg = rvu_read64(rvu, blkaddr, NPA_AF_LFX_AURAS_CFG(npalf));
404 	rvu_write64(rvu, blkaddr, NPA_AF_LFX_AURAS_CFG(npalf), cfg);
407 	rvu_write64(rvu, blkaddr, NPA_AF_LFX_LOC_AURAS_BASE(npalf),
411 	rvu_write64(rvu, blkaddr, NPA_AF_LFX_QINTS_CFG(npalf),
413 	rvu_write64(rvu, blkaddr, NPA_AF_LFX_QINTS_BASE(npalf),
424 	cfg = rvu_read64(rvu, blkaddr, NPA_AF_CONST);
443 	int blkaddr;
446 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, pcifunc);
447 	if (!pfvf->npalf || blkaddr < 0)
450 	block = &hw->block[blkaddr];
517 	int blkaddr;
519 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, 0);
520 	if (blkaddr < 0)
524 	return npa_aq_init(rvu, &hw->block[blkaddr]);
531 	int blkaddr;
533 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, 0);
534 	if (blkaddr < 0)
537 	block = &hw->block[blkaddr];
565 int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr)
571 	reg = rvu_read64(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL);
572 	rvu_write64(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL, reg & GENMASK_ULL(62, 0));
575 	err = rvu_poll_reg(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL, GENMASK_ULL(47, 32), true);
581 	ndc_af_const = rvu_read64(rvu, blkaddr, NDC_AF_CONST);
590 			reg = rvu_read64(rvu, blkaddr,
593 				rvu_write64(rvu, blkaddr,