octeontx2/af/rvu_cpt.c

29 		reg = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_STS(e)); \
44 	int blkaddr = block->addr;
49 	reg = rvu_read64(rvu, blkaddr, CPT_AF_FLTX_INT(vec));
65 		grp = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_CTL2(eng)) & 0xFF;
67 		rvu_write64(rvu, blkaddr, CPT_AF_EXEX_CTL2(eng), 0x0);
68 		val = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_CTL(eng));
69 		rvu_write64(rvu, blkaddr, CPT_AF_EXEX_CTL(eng), val & ~1ULL);
71 		rvu_write64(rvu, blkaddr, CPT_AF_EXEX_CTL2(eng), grp);
72 		rvu_write64(rvu, blkaddr, CPT_AF_EXEX_CTL(eng), val | 1ULL);
76 		val = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_STS(eng));
82 	rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT(vec), reg);
106 	int blkaddr = block->addr;
109 	reg = rvu_read64(rvu, blkaddr, CPT_AF_RVU_INT);
112 	rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT, reg);
120 	int blkaddr = block->addr;
123 	reg = rvu_read64(rvu, blkaddr, CPT_AF_RAS_INT);
126 	rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT, reg);
152 	int blkaddr = block->addr;
156 	rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1C(0), ~0ULL);
157 	rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1C(1), ~0ULL);
158 	rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1C(2), 0xFFFF);
160 	rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT_ENA_W1C, 0x1);
161 	rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT_ENA_W1C, 0x1);
170 static void cpt_unregister_interrupts(struct rvu *rvu, int blkaddr)
176 	if (!is_block_implemented(rvu->hw, blkaddr))
178 	offs = rvu_read64(rvu, blkaddr, CPT_PRIV_AF_INT_CFG) & 0x7FF;
184 	block = &hw->block[blkaddr];
190 		rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1C(i), ~0ULL);
191 	rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT_ENA_W1C, 0x1);
192 	rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT_ENA_W1C, 0x1);
210 	int blkaddr = block->addr;
233 			rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1S(i), 0xFFFF);
235 			rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1S(i), ~0ULL);
243 	rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT_ENA_W1S, 0x1);
250 	rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT_ENA_W1S, 0x1);
258 static int cpt_register_interrupts(struct rvu *rvu, int blkaddr)
265 	if (!is_block_implemented(rvu->hw, blkaddr))
268 	block = &hw->block[blkaddr];
269 	offs = rvu_read64(rvu, blkaddr, CPT_PRIV_AF_INT_CFG) & 0x7FF;
293 		rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1S(i), ~0ULL);
301 	rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT_ENA_W1S, 0x1);
308 	rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT_ENA_W1S, 0x1);
375 	int blkaddr;
377 	blkaddr = req_blkaddr ? req_blkaddr : BLKADDR_CPT0;
378 	if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1)
381 	return blkaddr;
390 	int cptlf, blkaddr;
394 	blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr);
395 	if (blkaddr < 0)
396 		return blkaddr;
401 	block = &rvu->hw->block[blkaddr];
439 		rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val);
444 		val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf));
448 		rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), val);
454 static int cpt_lf_free(struct rvu *rvu, struct msg_req *req, int blkaddr)
460 	block = &rvu->hw->block[blkaddr];
472 		rvu_cpt_lf_teardown(rvu, pcifunc, blkaddr, cptlf, slot);
477 			dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n",
500 static int cpt_inline_ipsec_cfg_inbound(struct rvu *rvu, int blkaddr, u8 cptlf,
507 	val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf));
519 	nix_sel = (blkaddr == BLKADDR_CPT1) ? 1 : 0;
527 	rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val);
531 		val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf));
534 		rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), val);
538 		rvu_write64(rvu, blkaddr, CPT_AF_ECO, 0x1);
547 		rvu_write64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(0), val);
548 		rvu_write64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(1), val);
554 static int cpt_inline_ipsec_cfg_outbound(struct rvu *rvu, int blkaddr, u8 cptlf,
562 	val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf));
580 	rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val);
584 		val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf));
586 		rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), val);
591 		val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf));
593 		rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val);
605 	int cptlf, blkaddr, ret;
608 	blkaddr = rvu_get_blkaddr_from_slot(rvu, BLKTYPE_CPT, pcifunc,
610 	if (blkaddr < 0)
613 	block = &rvu->hw->block[blkaddr];
621 		ret = cpt_inline_ipsec_cfg_inbound(rvu, blkaddr, cptlf, req);
625 		ret = cpt_inline_ipsec_cfg_outbound(rvu, blkaddr, cptlf, req);
638 	int blkaddr, num_lfs, lf;
642 	blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr);
643 	if (blkaddr < 0)
653 		block = &rvu->hw->block[blkaddr];
661 		lf = rvu_get_lf(rvu, &rvu->hw->block[blkaddr],
699 	int blkaddr;
701 	blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr);
702 	if (blkaddr < 0)
703 		return blkaddr;
718 		rvu_write64(rvu, blkaddr, req->reg_offset, req->val);
720 		rsp->val = rvu_read64(rvu, blkaddr, req->reg_offset);
725 static void get_ctx_pc(struct rvu *rvu, struct cpt_sts_rsp *rsp, int blkaddr)
730 	rsp->ctx_mis_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_MIS_PC);
731 	rsp->ctx_hit_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_HIT_PC);
732 	rsp->ctx_aop_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_AOP_PC);
733 	rsp->ctx_aop_lat_pc = rvu_read64(rvu, blkaddr,
735 	rsp->ctx_ifetch_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_IFETCH_PC);
736 	rsp->ctx_ifetch_lat_pc = rvu_read64(rvu, blkaddr,
738 	rsp->ctx_ffetch_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_FFETCH_PC);
739 	rsp->ctx_ffetch_lat_pc = rvu_read64(rvu, blkaddr,
741 	rsp->ctx_wback_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_FFETCH_PC);
742 	rsp->ctx_wback_lat_pc = rvu_read64(rvu, blkaddr,
744 	rsp->ctx_psh_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_FFETCH_PC);
745 	rsp->ctx_psh_lat_pc = rvu_read64(rvu, blkaddr,
747 	rsp->ctx_err = rvu_read64(rvu, blkaddr, CPT_AF_CTX_ERR);
748 	rsp->ctx_enc_id = rvu_read64(rvu, blkaddr, CPT_AF_CTX_ENC_ID);
749 	rsp->ctx_flush_timer = rvu_read64(rvu, blkaddr, CPT_AF_CTX_FLUSH_TIMER);
751 	rsp->rxc_time = rvu_read64(rvu, blkaddr, CPT_AF_RXC_TIME);
752 	rsp->rxc_time_cfg = rvu_read64(rvu, blkaddr, CPT_AF_RXC_TIME_CFG);
753 	rsp->rxc_active_sts = rvu_read64(rvu, blkaddr, CPT_AF_RXC_ACTIVE_STS);
754 	rsp->rxc_zombie_sts = rvu_read64(rvu, blkaddr, CPT_AF_RXC_ZOMBIE_STS);
755 	rsp->rxc_dfrg = rvu_read64(rvu, blkaddr, CPT_AF_RXC_DFRG);
756 	rsp->x2p_link_cfg0 = rvu_read64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(0));
757 	rsp->x2p_link_cfg1 = rvu_read64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(1));
760 static void get_eng_sts(struct rvu *rvu, struct cpt_sts_rsp *rsp, int blkaddr)
766 	reg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS1);
788 	int blkaddr;
790 	blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr);
791 	if (blkaddr < 0)
792 		return blkaddr;
799 	get_ctx_pc(rvu, rsp, blkaddr);
802 	get_eng_sts(rvu, rsp, blkaddr);
805 	rsp->inst_req_pc = rvu_read64(rvu, blkaddr, CPT_AF_INST_REQ_PC);
806 	rsp->inst_lat_pc = rvu_read64(rvu, blkaddr, CPT_AF_INST_LATENCY_PC);
807 	rsp->rd_req_pc = rvu_read64(rvu, blkaddr, CPT_AF_RD_REQ_PC);
808 	rsp->rd_lat_pc = rvu_read64(rvu, blkaddr, CPT_AF_RD_LATENCY_PC);
809 	rsp->rd_uc_pc = rvu_read64(rvu, blkaddr, CPT_AF_RD_UC_PC);
810 	rsp->active_cycles_pc = rvu_read64(rvu, blkaddr,
812 	rsp->exe_err_info = rvu_read64(rvu, blkaddr, CPT_AF_EXE_ERR_INFO);
813 	rsp->cptclk_cnt = rvu_read64(rvu, blkaddr, CPT_AF_CPTCLK_CNT);
814 	rsp->diag = rvu_read64(rvu, blkaddr, CPT_AF_DIAG);
827 			     int blkaddr, struct cpt_rxc_time_cfg_req *save)
833 		dfrg_reg = rvu_read64(rvu, blkaddr, CPT_AF_RXC_DFRG);
839 		save->step = rvu_read64(rvu, blkaddr, CPT_AF_RXC_TIME_CFG);
847 	rvu_write64(rvu, blkaddr, CPT_AF_RXC_TIME_CFG, req->step);
848 	rvu_write64(rvu, blkaddr, CPT_AF_RXC_DFRG, dfrg_reg);
855 	int blkaddr;
857 	blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr);
858 	if (blkaddr < 0)
859 		return blkaddr;
866 	cpt_rxc_time_cfg(rvu, req, blkaddr, NULL);
882 	int cptlf, blkaddr, ret;
886 	blkaddr = rvu_get_blkaddr_from_slot(rvu, BLKTYPE_CPT, pcifunc,
888 	if (blkaddr < 0)
891 	block = &rvu->hw->block[blkaddr];
896 	ctl = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf));
897 	ctl2 = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf));
901 		dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n",
904 	rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), ctl);
905 	rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), ctl2);
915 	int blkaddr, vec;
917 	blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr);
918 	if (blkaddr < 0)
919 		return blkaddr;
921 	block = &rvu->hw->block[blkaddr];
935 static void cpt_rxc_teardown(struct rvu *rvu, int blkaddr)
953 	cpt_rxc_time_cfg(rvu, &req, blkaddr, &prev);
956 		reg = rvu_read64(rvu, blkaddr, CPT_AF_RXC_ACTIVE_STS);
969 		reg = rvu_read64(rvu, blkaddr, CPT_AF_RXC_ZOMBIE_STS);
981 	cpt_rxc_time_cfg(rvu, &prev, blkaddr, NULL);
991 static void cpt_lf_disable_iqueue(struct rvu *rvu, int blkaddr, int slot)
999 	rvu_write64(rvu, blkaddr, CPT_AF_BAR2_ALIASX(slot, CPT_LF_CTL), 0x0);
1001 	inprog = rvu_read64(rvu, blkaddr,
1004 	rvu_write64(rvu, blkaddr,
1007 	qsize = rvu_read64(rvu, blkaddr,
1010 		inst_ptr = rvu_read64(rvu, blkaddr,
1025 		inprog = rvu_read64(rvu, blkaddr,
1043 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf, int slot)
1048 		cpt_rxc_teardown(rvu, blkaddr);
1053 	rvu_bar2_sel_write64(rvu, blkaddr, CPT_AF_BAR2_SEL, reg);
1055 	cpt_lf_disable_iqueue(rvu, blkaddr, slot);
1057 	rvu_bar2_sel_write64(rvu, blkaddr, CPT_AF_BAR2_SEL, 0);
1066 static int cpt_inline_inb_lf_cmd_send(struct rvu *rvu, int blkaddr,
1120 	cpt_idx = (blkaddr == BLKADDR_CPT0) ? 0 : 1;
1154 	int nix_blkaddr, blkaddr;
1167 	blkaddr = (nix_blkaddr == BLKADDR_NIX1) ? BLKADDR_CPT1 : BLKADDR_CPT0;
1172 	rc = cpt_inline_inb_lf_cmd_send(rvu, blkaddr, nix_blkaddr);
1177 	cpt_rxc_teardown(rvu, blkaddr);
1179 	reg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS0);
1185 					blkaddr);
1193 	rvu_bar2_sel_write64(rvu, blkaddr, CPT_AF_BAR2_SEL, reg);
1196 		cam_data = rvu_read64(rvu, blkaddr, CPT_AF_CTX_CAM_DATA(i));
1201 			rvu_write64(rvu, blkaddr,
1206 	rvu_bar2_sel_write64(rvu, blkaddr, CPT_AF_BAR2_SEL, 0);