octeontx2/af/mcs_cnf10kb.c

7 #include "mcs.h"
25 void cnf10kb_mcs_set_hw_capabilities(struct mcs *mcs)
27 	struct hwinfo *hw = mcs->hw;
33 	hw->lmac_cnt = 4;		/* lmacs/ports per mcs block */
39 void cnf10kb_mcs_parser_cfg(struct mcs *mcs)
47 	mcs_reg_write(mcs, reg, val);
50 	mcs_reg_write(mcs, reg, val);
57 	mcs_reg_write(mcs, reg, val);
61 	mcs_reg_write(mcs, reg, val);
67 	mcs_reg_write(mcs, reg, val);
70 	mcs_reg_write(mcs, reg, val);
73 void cnf10kb_mcs_flowid_secy_map(struct mcs *mcs, struct secy_mem_map *map, int dir)
82 		mcs_reg_write(mcs, reg, map->sci);
87 	mcs_reg_write(mcs, reg, val);
90 void cnf10kb_mcs_tx_sa_mem_map_write(struct mcs *mcs, struct mcs_tx_sc_sa_map *map)
97 	mcs_reg_write(mcs, reg, val);
100 	val = mcs_reg_read(mcs, reg);
107 	mcs_reg_write(mcs, reg, val);
109 	mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_SA_INDEX0_VLDX(map->sc_id), map->sa_index0_vld);
110 	mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_SA_INDEX1_VLDX(map->sc_id), map->sa_index1_vld);
112 	mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_TX_SA_ACTIVEX(map->sc_id), map->tx_sa_active);
115 void cnf10kb_mcs_rx_sa_mem_map_write(struct mcs *mcs, struct mcs_rx_sc_sa_map *map)
122 	mcs_reg_write(mcs, reg, val);
125 int mcs_set_force_clk_en(struct mcs *mcs, bool set)
130 	val = mcs_reg_read(mcs, MCSX_MIL_GLOBAL);
134 		mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val);
137 		while (!(mcs_reg_read(mcs, MCSX_MIL_IP_GBL_STATUS) & BIT_ULL(0))) {
139 				dev_err(mcs->dev, "MCS set force clk enable failed\n");
145 		mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val);
156 void cnf10kb_mcs_tx_pn_thresh_reached_handler(struct mcs *mcs)
164 	sc_bmap = &mcs->tx.sc;
166 	event.mcs_id = mcs->mcs_id;
169 	rekey_ena = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_AUTO_REKEY_ENABLE_0);
171 	for_each_set_bit(sc, sc_bmap->bmap, mcs->hw->sc_entries) {
175 		sa_status = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_TX_SA_ACTIVEX(sc));
177 		if (sa_status == mcs->tx_sa_active[sc])
181 		val = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_SA_MAP_MEM_0X(sc));
187 		event.pcifunc = mcs->tx.sa2pf_map[event.sa_id];
188 		mcs_add_intr_wq_entry(mcs, &event);
192 void cnf10kb_mcs_tx_pn_wrapped_handler(struct mcs *mcs)
199 	sc_bmap = &mcs->tx.sc;
201 	event.mcs_id = mcs->mcs_id;
204 	for_each_set_bit(sc, sc_bmap->bmap, mcs->hw->sc_entries) {
205 		val = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_SA_MAP_MEM_0X(sc));
207 		if (mcs->tx_sa_active[sc])
214 		event.pcifunc = mcs->tx.sa2pf_map[event.sa_id];
215 		mcs_add_intr_wq_entry(mcs, &event);
219 void cnf10kb_mcs_bbe_intr_handler(struct mcs *mcs, u64 intr,
228 	event.mcs_id = mcs->mcs_id;
229 	event.pcifunc = mcs->pf_map[0];
249 		mcs_add_intr_wq_entry(mcs, &event);
253 void cnf10kb_mcs_pab_intr_handler(struct mcs *mcs, u64 intr,
262 	event.mcs_id = mcs->mcs_id;
263 	event.pcifunc = mcs->pf_map[0];
275 		mcs_add_intr_wq_entry(mcs, &event);