marvell/octeon_ep_vf/octep_vf_cnxk.c

17 static void cnxk_vf_dump_q_regs(struct octep_vf_device *oct, int qno)
19 	struct device *dev = &oct->pdev->dev;
24 		 octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_INSTR_DBELL(qno)));
27 		 octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_CONTROL(qno)));
30 		 octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_ENABLE(qno)));
33 		 octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_INSTR_BADDR(qno)));
36 		 octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_INSTR_RSIZE(qno)));
39 		 octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_CNTS(qno)));
42 		 octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_INT_LEVELS(qno)));
45 		 octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_PKT_CNT(qno)));
48 		 octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_BYTE_CNT(qno)));
53 		 octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_DBELL(qno)));
56 		 octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(qno)));
59 		 octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_ENABLE(qno)));
62 		 octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_BADDR(qno)));
65 		 octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_RSIZE(qno)));
68 		 octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CNTS(qno)));
71 		 octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_INT_LEVELS(qno)));
74 		 octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_PKT_CNT(qno)));
77 		 octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_BYTE_CNT(qno)));
80 		 octep_vf_read_csr64(oct, CNXK_VF_SDP_R_ERR_TYPE(qno)));
84 static void cnxk_vf_reset_iq(struct octep_vf_device *oct, int q_no)
88 	dev_dbg(&oct->pdev->dev, "Reset VF IQ-%d\n", q_no);
91 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_ENABLE(q_no), val);
94 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INT_LEVELS(q_no), val);
95 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_PKT_CNT(q_no), val);
96 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_BYTE_CNT(q_no), val);
97 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INSTR_BADDR(q_no), val);
98 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INSTR_RSIZE(q_no), val);
101 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INSTR_DBELL(q_no), val);
103 	val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_CNTS(q_no));
104 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_CNTS(q_no), val & GENMASK_ULL(31, 0));
108 static void cnxk_vf_reset_oq(struct octep_vf_device *oct, int q_no)
113 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_ENABLE(q_no), val);
116 	val = octep_vf_read_csr(oct, CNXK_VF_SDP_R_OUT_CNTS(q_no));
117 	octep_vf_write_csr(oct, CNXK_VF_SDP_R_OUT_CNTS(q_no), val);
119 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_PKT_CNT(q_no), GENMASK_ULL(35, 0));
120 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_DBELL(q_no), GENMASK_ULL(31, 0));
124 static void octep_vf_reset_io_queues_cnxk(struct octep_vf_device *oct)
126 	struct pci_dev *pdev = oct->pdev;
131 	for (q = 0; q < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); q++) {
132 		cnxk_vf_reset_iq(oct, q);
133 		cnxk_vf_reset_oq(oct, q);
138 static void octep_vf_init_config_cnxk_vf(struct octep_vf_device *oct)
140 	struct octep_vf_config *conf = oct->conf;
143 	reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_CONTROL(0));
164 static void octep_vf_setup_iq_regs_cnxk(struct octep_vf_device *oct, int iq_no)
166 	struct octep_vf_iq *iq = oct->iq[iq_no];
170 	reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_CONTROL(iq_no));
175 			reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_CONTROL(iq_no));
181 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_CONTROL(iq_no), reg_val);
184 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INSTR_BADDR(iq_no), iq->desc_ring_dma);
185 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INSTR_RSIZE(iq_no), iq->max_count);
188 	iq->doorbell_reg = oct->mmio.hw_addr + CNXK_VF_SDP_R_IN_INSTR_DBELL(iq_no);
189 	iq->inst_cnt_reg = oct->mmio.hw_addr + CNXK_VF_SDP_R_IN_CNTS(iq_no);
190 	iq->intr_lvl_reg = oct->mmio.hw_addr + CNXK_VF_SDP_R_IN_INT_LEVELS(iq_no);
197 	reg_val = CFG_GET_IQ_INTR_THRESHOLD(oct->conf) & GENMASK_ULL(31, 0);
198 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INT_LEVELS(iq_no), reg_val);
202 static void octep_vf_setup_oq_regs_cnxk(struct octep_vf_device *oct, int oq_no)
204 	struct octep_vf_oq *oq = oct->oq[oq_no];
209 	reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no));
214 			reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no));
229 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no), reg_val);
230 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_BADDR(oq_no), oq->desc_ring_dma);
231 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_RSIZE(oq_no), oq->max_count);
233 	oq_ctl = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no));
238 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no), oq_ctl);
241 	oq->pkts_sent_reg = oct->mmio.hw_addr + CNXK_VF_SDP_R_OUT_CNTS(oq_no);
242 	oq->pkts_credit_reg = oct->mmio.hw_addr + CNXK_VF_SDP_R_OUT_SLIST_DBELL(oq_no);
244 	time_threshold = CFG_GET_OQ_INTR_TIME(oct->conf);
245 	reg_val = ((u64)time_threshold << 32) | CFG_GET_OQ_INTR_PKT(oct->conf);
246 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_INT_LEVELS(oq_no), reg_val);
249 	reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_WMARK(oq_no));
251 	reg_val |= CFG_GET_OQ_WMARK(oct->conf);
252 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_WMARK(oq_no), reg_val);
256 static void octep_vf_setup_mbox_regs_cnxk(struct octep_vf_device *oct, int q_no)
258 	struct octep_vf_mbox *mbox = oct->mbox;
261 	mbox->mbox_read_reg = oct->mmio.hw_addr + CNXK_VF_SDP_R_MBOX_PF_VF_DATA(q_no);
264 	mbox->mbox_int_reg = oct->mmio.hw_addr + CNXK_VF_SDP_R_MBOX_PF_VF_INT(q_no);
267 	mbox->mbox_write_reg = oct->mmio.hw_addr + CNXK_VF_SDP_R_MBOX_VF_PF_DATA(q_no);
271 static void cnxk_handle_vf_mbox_intr(struct octep_vf_device *oct)
273 	if (oct->mbox)
274 		schedule_work(&oct->mbox->wk.work);
276 		dev_err(&oct->pdev->dev, "cannot schedule work on invalid mbox\n");
283 	struct octep_vf_device *oct;
287 	oct = vector->octep_vf_dev;
291 		reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_MBOX_PF_VF_INT(0));
293 			cnxk_handle_vf_mbox_intr(oct);
294 			octep_vf_write_csr64(oct, CNXK_VF_SDP_R_MBOX_PF_VF_INT(0), reg_val);
302 static void octep_vf_reinit_regs_cnxk(struct octep_vf_device *oct)
306 	for (i = 0; i < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); i++)
307 		oct->hw_ops.setup_iq_regs(oct, i);
309 	for (i = 0; i < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); i++)
310 		oct->hw_ops.setup_oq_regs(oct, i);
312 	oct->hw_ops.enable_interrupts(oct);
313 	oct->hw_ops.enable_io_queues(oct);
315 	for (i = 0; i < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); i++)
316 		writel(oct->oq[i]->max_count, oct->oq[i]->pkts_credit_reg);
320 static void octep_vf_enable_interrupts_cnxk(struct octep_vf_device *oct)
325 	num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf);
327 		reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_INT_LEVELS(q));
329 		octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INT_LEVELS(q), reg_val);
331 		reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_INT_LEVELS(q));
333 		octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_INT_LEVELS(q), reg_val);
336 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_MBOX_PF_VF_INT(0),
341 static void octep_vf_disable_interrupts_cnxk(struct octep_vf_device *oct)
347 	if (oct->mbox)
348 		octep_vf_write_csr64(oct, CNXK_VF_SDP_R_MBOX_PF_VF_INT(0), 0x0);
350 	num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf);
352 		reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_INT_LEVELS(q));
354 		octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INT_LEVELS(q), reg_val);
356 		reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_INT_LEVELS(q));
358 		octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_INT_LEVELS(q), reg_val);
377 static void octep_vf_enable_iq_cnxk(struct octep_vf_device *oct, int iq_no)
382 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INSTR_DBELL(iq_no), GENMASK_ULL(31, 0));
384 	while (octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_INSTR_DBELL(iq_no)) &&
389 	reg_val = octep_vf_read_csr64(oct,  CNXK_VF_SDP_R_IN_INT_LEVELS(iq_no));
391 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INT_LEVELS(iq_no), reg_val);
393 	reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_ENABLE(iq_no));
395 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_ENABLE(iq_no), reg_val);
399 static void octep_vf_enable_oq_cnxk(struct octep_vf_device *oct, int oq_no)
403 	reg_val = octep_vf_read_csr64(oct,  CNXK_VF_SDP_R_OUT_INT_LEVELS(oq_no));
405 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_INT_LEVELS(oq_no), reg_val);
407 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_DBELL(oq_no), GENMASK_ULL(31, 0));
409 	reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_ENABLE(oq_no));
411 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_ENABLE(oq_no), reg_val);
415 static void octep_vf_enable_io_queues_cnxk(struct octep_vf_device *oct)
419 	for (q = 0; q < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); q++) {
420 		octep_vf_enable_iq_cnxk(oct, q);
421 		octep_vf_enable_oq_cnxk(oct, q);
426 static void octep_vf_disable_iq_cnxk(struct octep_vf_device *oct, int iq_no)
430 	reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_ENABLE(iq_no));
432 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_ENABLE(iq_no), reg_val);
436 static void octep_vf_disable_oq_cnxk(struct octep_vf_device *oct, int oq_no)
440 	reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_ENABLE(oq_no));
442 	octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_ENABLE(oq_no), reg_val);
446 static void octep_vf_disable_io_queues_cnxk(struct octep_vf_device *oct)
450 	for (q = 0; q < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); q++) {
451 		octep_vf_disable_iq_cnxk(oct, q);
452 		octep_vf_disable_oq_cnxk(oct, q);
457 static void octep_vf_dump_registers_cnxk(struct octep_vf_device *oct)
461 	num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf);
463 		cnxk_vf_dump_q_regs(oct, q);
469  * @oct: Octeon device private data structure.
475 void octep_vf_device_setup_cnxk(struct octep_vf_device *oct)
477 	oct->hw_ops.setup_iq_regs = octep_vf_setup_iq_regs_cnxk;
478 	oct->hw_ops.setup_oq_regs = octep_vf_setup_oq_regs_cnxk;
479 	oct->hw_ops.setup_mbox_regs = octep_vf_setup_mbox_regs_cnxk;
481 	oct->hw_ops.ioq_intr_handler = octep_vf_ioq_intr_handler_cnxk;
482 	oct->hw_ops.reinit_regs = octep_vf_reinit_regs_cnxk;
484 	oct->hw_ops.enable_interrupts = octep_vf_enable_interrupts_cnxk;
485 	oct->hw_ops.disable_interrupts = octep_vf_disable_interrupts_cnxk;
487 	oct->hw_ops.update_iq_read_idx = octep_vf_update_iq_read_index_cnxk;
489 	oct->hw_ops.enable_iq = octep_vf_enable_iq_cnxk;
490 	oct->hw_ops.enable_oq = octep_vf_enable_oq_cnxk;
491 	oct->hw_ops.enable_io_queues = octep_vf_enable_io_queues_cnxk;
493 	oct->hw_ops.disable_iq = octep_vf_disable_iq_cnxk;
494 	oct->hw_ops.disable_oq = octep_vf_disable_oq_cnxk;
495 	oct->hw_ops.disable_io_queues = octep_vf_disable_io_queues_cnxk;
496 	oct->hw_ops.reset_io_queues = octep_vf_reset_io_queues_cnxk;
498 	oct->hw_ops.dump_registers = octep_vf_dump_registers_cnxk;
499 	octep_vf_init_config_cnxk_vf(oct);