marvell/octeon_ep/octep_cnxk_pf.c

127 static int cnxk_reset_iq(struct octep_device *oct, int q_no)
132 	dev_dbg(&oct->pdev->dev, "Reset PF IQ-%d\n", q_no);
135 	q_no += conf->pf_ring_cfg.srn;
138 	octep_write_csr64(oct, CNXK_SDP_R_IN_ENABLE(q_no), val);
141 	octep_write_csr64(oct, CNXK_SDP_R_IN_CNTS(q_no), val);
142 	octep_write_csr64(oct, CNXK_SDP_R_IN_INT_LEVELS(q_no), val);
143 	octep_write_csr64(oct, CNXK_SDP_R_IN_PKT_CNT(q_no), val);
144 	octep_write_csr64(oct, CNXK_SDP_R_IN_BYTE_CNT(q_no), val);
145 	octep_write_csr64(oct, CNXK_SDP_R_IN_INSTR_BADDR(q_no), val);
146 	octep_write_csr64(oct, CNXK_SDP_R_IN_INSTR_RSIZE(q_no), val);
149 	octep_write_csr64(oct, CNXK_SDP_R_IN_INSTR_DBELL(q_no), val);
155 static void cnxk_reset_oq(struct octep_device *oct, int q_no)
159 	q_no += CFG_GET_PORTS_PF_SRN(oct->conf);
162 	octep_write_csr64(oct, CNXK_SDP_R_OUT_ENABLE(q_no), val);
163 	octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(q_no), val);
164 	octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_RSIZE(q_no), val);
165 	octep_write_csr64(oct, CNXK_SDP_R_OUT_INT_LEVELS(q_no), val);
168 	val = octep_read_csr(oct, CNXK_SDP_R_OUT_CNTS(q_no));
169 	octep_write_csr(oct, CNXK_SDP_R_OUT_CNTS(q_no), val);
171 	octep_write_csr64(oct, CNXK_SDP_R_OUT_PKT_CNT(q_no), 0xFFFFFFFFFULL);
172 	octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_DBELL(q_no), 0xFFFFFFFF);
391 static void octep_setup_mbox_regs_cnxk_pf(struct octep_device *oct, int q_no)
393 	struct octep_mbox *mbox = oct->mbox[q_no];
396 	mbox->pf_vf_data_reg = oct->mmio[0].hw_addr + CNXK_SDP_MBOX_PF_VF_DATA(q_no);
399 	mbox->vf_pf_data_reg = oct->mmio[0].hw_addr + CNXK_SDP_MBOX_VF_PF_DATA(q_no);