marvell/mvpp2/mvpp2_prs.c

47 			   int tid)
51 	if (tid > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
55 	pe->index = tid;
367 	int tid;
370 	for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
373 		if (!priv->prs_shadow[tid].valid ||
374 		    priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
377 		mvpp2_prs_init_from_hw(priv, &pe, tid);
382 			return tid;
392 	int tid;
397 	for (tid = start; tid <= end; tid++) {
398 		if (!priv->prs_shadow[tid].valid)
399 			return tid;
478 	int tid;
482 		tid = MVPP2_PE_MAC_UC_PROMISCUOUS;
486 		tid = MVPP2_PE_MAC_MC_PROMISCUOUS;
491 	if (priv->prs_shadow[tid].valid) {
492 		mvpp2_prs_init_from_hw(priv, &pe, tid);
496 		pe.index = tid;
530 	int tid, shift;
533 		tid = tagged ? MVPP2_PE_EDSA_TAGGED : MVPP2_PE_EDSA_UNTAGGED;
536 		tid = tagged ? MVPP2_PE_DSA_TAGGED : MVPP2_PE_DSA_UNTAGGED;
540 	if (priv->prs_shadow[tid].valid) {
542 		mvpp2_prs_init_from_hw(priv, &pe, tid);
547 		pe.index = tid;
597 	int tid, shift, port_mask;
600 		tid = tagged ? MVPP2_PE_ETYPE_EDSA_TAGGED :
605 		tid = tagged ? MVPP2_PE_ETYPE_DSA_TAGGED :
611 	if (priv->prs_shadow[tid].valid) {
613 		mvpp2_prs_init_from_hw(priv, &pe, tid);
618 		pe.index = tid;
664 	int tid;
667 	for (tid = MVPP2_PE_FIRST_FREE_TID;
668 	     tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
672 		if (!priv->prs_shadow[tid].valid ||
673 		    priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VLAN)
676 		mvpp2_prs_init_from_hw(priv, &pe, tid);
695 			return tid;
706 	int tid_aux, tid;
711 	tid = mvpp2_prs_vlan_find(priv, tpid, ai);
713 	if (tid < 0) {
715 		tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_LAST_FREE_TID,
717 		if (tid < 0)
718 			return tid;
720 		/* Get last double vlan tid */
736 		if (tid <= tid_aux)
740 		pe.index = tid;
763 		mvpp2_prs_init_from_hw(priv, &pe, tid);
791 	int tid;
794 	for (tid = MVPP2_PE_FIRST_FREE_TID;
795 	     tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
799 		if (!priv->prs_shadow[tid].valid ||
800 		    priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VLAN)
803 		mvpp2_prs_init_from_hw(priv, &pe, tid);
813 			return tid;
824 	int tid_aux, tid, ai, ret = 0;
829 	tid = mvpp2_prs_double_vlan_find(priv, tpid1, tpid2);
831 	if (tid < 0) {
833 		tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
835 		if (tid < 0)
836 			return tid;
843 		/* Get first single/triple vlan tid */
860 		if (tid >= tid_aux)
865 		pe.index = tid;
883 		mvpp2_prs_init_from_hw(priv, &pe, tid);
898 	int tid;
905 	tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
907 	if (tid < 0)
908 		return tid;
912 	pe.index = tid;
940 	tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
942 	if (tid < 0)
943 		return tid;
945 	pe.index = tid;
968 	int mask, tid;
970 	tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
972 	if (tid < 0)
973 		return tid;
977 	pe.index = tid;
1025 	int tid;
1031 	tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1033 	if (tid < 0)
1034 		return tid;
1038 	pe.index = tid;
1065 	int tid;
1070 	tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1072 	if (tid < 0)
1073 		return tid;
1077 	pe.index = tid;
1334 	int tid, ihl;
1337 	tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1339 	if (tid < 0)
1340 		return tid;
1344 	pe.index = tid;
1363 	tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1365 	if (tid < 0)
1366 		return tid;
1370 	pe.index = tid;
1393 	tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1395 	if (tid < 0)
1396 		return tid;
1400 	pe.index = tid;
1428 		tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1430 		if (tid < 0)
1431 			return tid;
1435 		pe.index = tid;
1465 	tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1467 	if (tid < 0)
1468 		return tid;
1472 	pe.index = tid;
1610 	int tid, ihl;
1614 		tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1616 		if (tid < 0)
1617 			return tid;
1621 		pe.index = tid;
1651 	tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1653 	if (tid < 0)
1654 		return tid;
1658 	pe.index = tid;
1679 	tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1681 	if (tid < 0)
1682 		return tid;
1686 	pe.index = tid;
1798 	int tid, err;
1835 	tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1837 	if (tid < 0)
1838 		return tid;
1842 	pe.index = tid;
1935 	int tid;
1938 	for (tid = MVPP2_PRS_VID_PORT_FIRST(port->id);
1939 	     tid <= MVPP2_PRS_VID_PORT_LAST(port->id); tid++) {
1940 		if (!port->priv->prs_shadow[tid].valid ||
1941 		    port->priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VID)
1944 		mvpp2_prs_init_from_hw(port->priv, &pe, tid);
1955 		return tid;
1969 	int tid;
1974 	tid = mvpp2_prs_vid_range_find(port, vid, mask);
1983 	if (tid < 0) {
1986 		tid = mvpp2_prs_tcam_first_free(priv, vid_start,
1991 		if (tid < 0)
1992 			return tid;
1995 		pe.index = tid;
2000 		mvpp2_prs_init_from_hw(priv, &pe, tid);
2029 	int tid;
2032 	tid = mvpp2_prs_vid_range_find(port, vid, 0xfff);
2035 	if (tid < 0)
2038 	mvpp2_prs_hw_inv(priv, tid);
2039 	priv->prs_shadow[tid].valid = false;
2046 	int tid;
2048 	for (tid = MVPP2_PRS_VID_PORT_FIRST(port->id);
2049 	     tid <= MVPP2_PRS_VID_PORT_LAST(port->id); tid++) {
2050 		if (priv->prs_shadow[tid].valid) {
2051 			mvpp2_prs_hw_inv(priv, tid);
2052 			priv->prs_shadow[tid].valid = false;
2060 	unsigned int tid = MVPP2_PRS_VID_PORT_DFLT(port->id);
2064 	mvpp2_prs_hw_inv(priv, tid);
2066 	priv->prs_shadow[tid].valid = false;
2072 	unsigned int tid = MVPP2_PRS_VID_PORT_DFLT(port->id);
2077 	if (priv->prs_shadow[tid].valid)
2082 	pe.index = tid;
2208 	int tid;
2211 	for (tid = MVPP2_PE_MAC_RANGE_START;
2212 	     tid <= MVPP2_PE_MAC_RANGE_END; tid++) {
2215 		if (!priv->prs_shadow[tid].valid ||
2216 		    (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
2217 		    (priv->prs_shadow[tid].udf != udf_type))
2220 		mvpp2_prs_init_from_hw(priv, &pe, tid);
2225 			return tid;
2238 	int tid;
2243 	tid = mvpp2_prs_mac_da_range_find(priv, BIT(port->id), da, mask,
2247 	if (tid < 0) {
2253 		tid = mvpp2_prs_tcam_first_free(priv,
2256 		if (tid < 0)
2257 			return tid;
2259 		pe.index = tid;
2264 		mvpp2_prs_init_from_hw(priv, &pe, tid);
2346 	int index, tid;
2348 	for (tid = MVPP2_PE_MAC_RANGE_START;
2349 	     tid <= MVPP2_PE_MAC_RANGE_END; tid++) {
2352 		if (!priv->prs_shadow[tid].valid ||
2353 		    (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
2354 		    (priv->prs_shadow[tid].udf != MVPP2_PRS_UDF_MAC_DEF))
2357 		mvpp2_prs_init_from_hw(priv, &pe, tid);
2436 	int tid, i;
2440 	tid = mvpp2_prs_tcam_first_free(priv,
2443 	if (tid < 0)
2444 		return tid;
2446 	pe.index = tid;
2471 	int tid;
2475 	tid = mvpp2_prs_flow_find(port->priv, port->id);
2478 	if (tid < 0) {
2480 		tid = mvpp2_prs_tcam_first_free(port->priv,
2483 		if (tid < 0)
2484 			return tid;
2486 		pe.index = tid;
2495 		mvpp2_prs_init_from_hw(port->priv, &pe, tid);