Lines Matching refs:pe
22 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
26 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
30 pe->tcam[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
33 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
35 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram[i]);
38 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
40 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam[i]);
46 int mvpp2_prs_init_from_hw(struct mvpp2 *priv, struct mvpp2_prs_entry *pe,
54 memset(pe, 0, sizeof(*pe));
55 pe->index = tid;
58 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
60 pe->tcam[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
62 if (pe->tcam[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
66 pe->tcam[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
69 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
71 pe->sram[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
101 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
103 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] &= ~MVPP2_PRS_TCAM_LU(MVPP2_PRS_LU_MASK);
104 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] &= ~MVPP2_PRS_TCAM_LU_EN(MVPP2_PRS_LU_MASK);
105 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] |= MVPP2_PRS_TCAM_LU(lu & MVPP2_PRS_LU_MASK);
106 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] |= MVPP2_PRS_TCAM_LU_EN(MVPP2_PRS_LU_MASK);
110 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
114 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT_EN(BIT(port));
116 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] |= MVPP2_PRS_TCAM_PORT_EN(BIT(port));
120 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
123 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT(MVPP2_PRS_PORT_MASK);
124 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT_EN(MVPP2_PRS_PORT_MASK);
125 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] |= MVPP2_PRS_TCAM_PORT_EN(~ports & MVPP2_PRS_PORT_MASK);
129 unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
131 return (~pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] >> 24) & MVPP2_PRS_PORT_MASK;
135 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
141 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] &= ~(0xff << pos);
142 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] &= ~(MVPP2_PRS_TCAM_EN(0xff) << pos);
143 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] |= byte << pos;
144 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] |= MVPP2_PRS_TCAM_EN(enable << pos);
148 void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
154 *byte = (pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] >> pos) & 0xff;
155 *enable = (pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] >> (pos + 16)) & 0xff;
159 static bool mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry *pe, int offs,
164 tcam_data = pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] & 0xffff;
169 static void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe,
179 pe->tcam[MVPP2_PRS_TCAM_AI_WORD] |= BIT(i);
181 pe->tcam[MVPP2_PRS_TCAM_AI_WORD] &= ~BIT(i);
184 pe->tcam[MVPP2_PRS_TCAM_AI_WORD] |= MVPP2_PRS_TCAM_AI_EN(enable);
188 static int mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry *pe)
190 return pe->tcam[MVPP2_PRS_TCAM_AI_WORD] & MVPP2_PRS_AI_MASK;
194 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
197 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
198 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
202 static void mvpp2_prs_match_vid(struct mvpp2_prs_entry *pe, int offset,
205 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, (vid & 0xf00) >> 8, 0xf);
206 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, vid & 0xff, 0xff);
210 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
213 pe->sram[MVPP2_BIT_TO_WORD(bit_num)] |= (val << (MVPP2_BIT_IN_WORD(bit_num)));
217 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
220 pe->sram[MVPP2_BIT_TO_WORD(bit_num)] &= ~(val << (MVPP2_BIT_IN_WORD(bit_num)));
224 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
234 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_OFFS + i,
237 mvpp2_prs_sram_bits_clear(pe,
241 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
246 static int mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry *pe)
248 return pe->sram[MVPP2_PRS_SRAM_RI_WORD];
252 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
262 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_OFFS + i,
265 mvpp2_prs_sram_bits_clear(pe,
269 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
274 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
281 bits = (pe->sram[ai_off] >> ai_shift) |
282 (pe->sram[ai_off + 1] << (32 - ai_shift));
290 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
295 mvpp2_prs_sram_bits_clear(pe, sram_next_off,
297 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
303 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
308 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
311 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
315 pe->sram[MVPP2_BIT_TO_WORD(MVPP2_PRS_SRAM_SHIFT_OFFS)] |=
319 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
321 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
324 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
330 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
336 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
339 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
343 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
345 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS,
349 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
351 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
354 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
356 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
360 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
366 struct mvpp2_prs_entry pe;
377 mvpp2_prs_init_from_hw(priv, &pe, tid);
378 bits = mvpp2_prs_sram_ai_get(&pe);
409 struct mvpp2_prs_entry pe;
412 memset(&pe, 0, sizeof(pe));
415 pe.index = MVPP2_PE_FC_DROP;
416 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
421 mvpp2_prs_tcam_data_byte_set(&pe, len, da[len], 0xff);
423 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
426 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
427 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
430 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
433 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
434 mvpp2_prs_hw_write(priv, &pe);
440 struct mvpp2_prs_entry pe;
444 mvpp2_prs_init_from_hw(priv, &pe, MVPP2_PE_DROP_ALL);
447 memset(&pe, 0, sizeof(pe));
448 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
449 pe.index = MVPP2_PE_DROP_ALL;
452 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
455 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
456 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
459 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
462 mvpp2_prs_tcam_port_map_set(&pe, 0);
466 mvpp2_prs_tcam_port_set(&pe, port, add);
468 mvpp2_prs_hw_write(priv, &pe);
475 struct mvpp2_prs_entry pe;
492 mvpp2_prs_init_from_hw(priv, &pe, tid);
494 memset(&pe, 0, sizeof(pe));
495 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
496 pe.index = tid;
499 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
502 mvpp2_prs_sram_ri_update(&pe, ri, MVPP2_PRS_RI_L2_CAST_MASK);
505 mvpp2_prs_tcam_data_byte_set(&pe, 0, cast_match,
509 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
513 mvpp2_prs_tcam_port_map_set(&pe, 0);
516 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
520 mvpp2_prs_tcam_port_set(&pe, port, add);
522 mvpp2_prs_hw_write(priv, &pe);
529 struct mvpp2_prs_entry pe;
542 mvpp2_prs_init_from_hw(priv, &pe, tid);
545 memset(&pe, 0, sizeof(pe));
546 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);
547 pe.index = tid;
550 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA);
554 mvpp2_prs_tcam_data_byte_set(&pe, 0,
560 mvpp2_prs_sram_ai_update(&pe, 1,
563 mvpp2_prs_sram_ai_update(&pe, 0,
567 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_SINGLE,
570 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID);
573 mvpp2_prs_sram_shift_set(&pe, shift,
577 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,
579 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
583 mvpp2_prs_tcam_port_map_set(&pe, 0);
587 mvpp2_prs_tcam_port_set(&pe, port, add);
589 mvpp2_prs_hw_write(priv, &pe);
596 struct mvpp2_prs_entry pe;
613 mvpp2_prs_init_from_hw(priv, &pe, tid);
616 memset(&pe, 0, sizeof(pe));
617 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);
618 pe.index = tid;
621 mvpp2_prs_match_etype(&pe, 0, ETH_P_EDSA);
622 mvpp2_prs_match_etype(&pe, 2, 0);
624 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DSA_MASK,
627 mvpp2_prs_sram_shift_set(&pe, 2 + MVPP2_ETH_TYPE_LEN + shift,
631 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA);
635 mvpp2_prs_tcam_data_byte_set(&pe,
640 mvpp2_prs_sram_ai_update(&pe, 0,
643 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);
646 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,
648 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
651 mvpp2_prs_tcam_port_map_set(&pe, port_mask);
655 mvpp2_prs_tcam_port_set(&pe, port, add);
657 mvpp2_prs_hw_write(priv, &pe);
663 struct mvpp2_prs_entry pe;
676 mvpp2_prs_init_from_hw(priv, &pe, tid);
677 match = mvpp2_prs_tcam_data_cmp(&pe, 0, tpid);
682 ri_bits = mvpp2_prs_sram_ri_get(&pe);
686 ai_bits = mvpp2_prs_tcam_ai_get(&pe);
705 struct mvpp2_prs_entry pe;
709 memset(&pe, 0, sizeof(pe));
729 mvpp2_prs_init_from_hw(priv, &pe, tid_aux);
730 ri_bits = mvpp2_prs_sram_ri_get(&pe);
739 memset(&pe, 0, sizeof(pe));
740 pe.index = tid;
741 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);
743 mvpp2_prs_match_etype(&pe, 0, tpid);
746 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID);
749 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
752 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_SINGLE,
756 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_TRIPLE,
759 mvpp2_prs_tcam_ai_update(&pe, ai, MVPP2_PRS_SRAM_AI_MASK);
761 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);
763 mvpp2_prs_init_from_hw(priv, &pe, tid);
766 mvpp2_prs_tcam_port_map_set(&pe, port_map);
768 mvpp2_prs_hw_write(priv, &pe);
790 struct mvpp2_prs_entry pe;
803 mvpp2_prs_init_from_hw(priv, &pe, tid);
805 match = mvpp2_prs_tcam_data_cmp(&pe, 0, tpid1) &&
806 mvpp2_prs_tcam_data_cmp(&pe, 4, tpid2);
811 ri_mask = mvpp2_prs_sram_ri_get(&pe) & MVPP2_PRS_RI_VLAN_MASK;
825 struct mvpp2_prs_entry pe;
827 memset(&pe, 0, sizeof(pe));
852 mvpp2_prs_init_from_hw(priv, &pe, tid_aux);
853 ri_bits = mvpp2_prs_sram_ri_get(&pe);
863 memset(&pe, 0, sizeof(pe));
864 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);
865 pe.index = tid;
869 mvpp2_prs_match_etype(&pe, 0, tpid1);
870 mvpp2_prs_match_etype(&pe, 4, tpid2);
872 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);
874 mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN,
876 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE,
878 mvpp2_prs_sram_ai_update(&pe, ai | MVPP2_PRS_DBL_VLAN_AI_BIT,
881 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);
883 mvpp2_prs_init_from_hw(priv, &pe, tid);
887 mvpp2_prs_tcam_port_map_set(&pe, port_map);
888 mvpp2_prs_hw_write(priv, &pe);
897 struct mvpp2_prs_entry pe;
910 memset(&pe, 0, sizeof(pe));
911 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
912 pe.index = tid;
915 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
916 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
919 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, -4,
921 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);
922 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask | MVPP2_PRS_RI_IP_FRAG_MASK);
924 mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00,
926 mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00,
929 mvpp2_prs_tcam_data_byte_set(&pe, 5, proto, MVPP2_PRS_TCAM_PROTO_MASK);
930 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
933 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
936 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
937 mvpp2_prs_hw_write(priv, &pe);
945 pe.index = tid;
947 pe.sram[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
948 pe.sram[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
949 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask);
951 mvpp2_prs_sram_ri_update(&pe, ri | MVPP2_PRS_RI_IP_FRAG_TRUE,
954 mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, 0x0);
955 mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, 0x0);
958 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
959 mvpp2_prs_hw_write(priv, &pe);
967 struct mvpp2_prs_entry pe;
975 memset(&pe, 0, sizeof(pe));
976 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
977 pe.index = tid;
981 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV4_MC,
983 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST,
988 mvpp2_prs_tcam_data_byte_set(&pe, 0, mask, mask);
989 mvpp2_prs_tcam_data_byte_set(&pe, 1, mask, mask);
990 mvpp2_prs_tcam_data_byte_set(&pe, 2, mask, mask);
991 mvpp2_prs_tcam_data_byte_set(&pe, 3, mask, mask);
992 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_BCAST,
1000 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
1002 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
1006 mvpp2_prs_sram_shift_set(&pe, -12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1008 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);
1011 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1014 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
1015 mvpp2_prs_hw_write(priv, &pe);
1024 struct mvpp2_prs_entry pe;
1036 memset(&pe, 0, sizeof(pe));
1037 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
1038 pe.index = tid;
1041 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1042 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1043 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask);
1044 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
1048 mvpp2_prs_tcam_data_byte_set(&pe, 0, proto, MVPP2_PRS_TCAM_PROTO_MASK);
1049 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
1052 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1055 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);
1056 mvpp2_prs_hw_write(priv, &pe);
1064 struct mvpp2_prs_entry pe;
1075 memset(&pe, 0, sizeof(pe));
1076 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
1077 pe.index = tid;
1080 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
1081 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST,
1083 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
1086 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1088 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV6_MC,
1090 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
1092 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1095 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);
1096 mvpp2_prs_hw_write(priv, &pe);
1131 struct mvpp2_prs_entry pe;
1135 memset(&pe, 0, sizeof(pe));
1136 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1137 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
1140 mvpp2_prs_tcam_port_map_set(&pe, 0);
1143 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
1144 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
1147 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
1148 mvpp2_prs_hw_write(priv, &pe);
1155 struct mvpp2_prs_entry pe;
1157 memset(&pe, 0, sizeof(pe));
1159 pe.index = MVPP2_PE_MH_DEFAULT;
1160 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
1161 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1163 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
1166 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1169 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
1170 mvpp2_prs_hw_write(priv, &pe);
1173 pe.index = MVPP2_PE_MH_SKIP_PRS;
1174 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
1175 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1177 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1178 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1181 mvpp2_prs_tcam_port_map_set(&pe, 0);
1184 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
1185 mvpp2_prs_hw_write(priv, &pe);
1193 struct mvpp2_prs_entry pe;
1195 memset(&pe, 0, sizeof(pe));
1198 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
1199 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1201 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1203 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1204 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1207 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1210 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1211 mvpp2_prs_hw_write(priv, &pe);
1223 struct mvpp2_prs_entry pe;
1256 memset(&pe, 0, sizeof(pe));
1257 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);
1258 pe.index = MVPP2_PE_DSA_DEFAULT;
1259 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);
1262 mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1263 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1266 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
1269 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1271 mvpp2_prs_hw_write(priv, &pe);
1277 struct mvpp2_prs_entry pe;
1279 memset(&pe, 0, sizeof(pe));
1282 pe.index = MVPP2_PE_VID_FLTR_DEFAULT;
1283 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID);
1285 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_EDSA_VID_AI_BIT);
1288 mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN,
1292 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
1294 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
1297 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1300 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID);
1301 mvpp2_prs_hw_write(priv, &pe);
1304 memset(&pe, 0, sizeof(pe));
1307 pe.index = MVPP2_PE_VID_EDSA_FLTR_DEFAULT;
1308 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID);
1310 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_EDSA_VID_AI_BIT,
1314 mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_EDSA_LEN,
1318 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
1320 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
1323 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1326 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID);
1327 mvpp2_prs_hw_write(priv, &pe);
1333 struct mvpp2_prs_entry pe;
1342 memset(&pe, 0, sizeof(pe));
1343 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1344 pe.index = tid;
1346 mvpp2_prs_match_etype(&pe, 0, ETH_P_PPP_SES);
1348 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
1350 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1351 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
1355 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1356 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1357 priv->prs_shadow[pe.index].finish = false;
1358 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
1360 mvpp2_prs_hw_write(priv, &pe);
1368 memset(&pe, 0, sizeof(pe));
1369 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1370 pe.index = tid;
1372 mvpp2_prs_match_etype(&pe, 0, ETH_P_ARP);
1375 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1376 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1377 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
1380 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1385 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1386 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1387 priv->prs_shadow[pe.index].finish = true;
1388 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
1390 mvpp2_prs_hw_write(priv, &pe);
1398 memset(&pe, 0, sizeof(pe));
1399 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1400 pe.index = tid;
1402 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
1405 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1406 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1407 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
1412 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1417 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1418 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1419 priv->prs_shadow[pe.index].finish = true;
1420 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
1424 mvpp2_prs_hw_write(priv, &pe);
1433 memset(&pe, 0, sizeof(pe));
1434 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1435 pe.index = tid;
1437 mvpp2_prs_match_etype(&pe, 0, ETH_P_IP);
1438 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
1443 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
1444 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
1447 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN +
1451 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
1456 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1457 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1458 priv->prs_shadow[pe.index].finish = false;
1459 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
1461 mvpp2_prs_hw_write(priv, &pe);
1470 memset(&pe, 0, sizeof(pe));
1471 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1472 pe.index = tid;
1474 mvpp2_prs_match_etype(&pe, 0, ETH_P_IPV6);
1477 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
1480 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
1481 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
1484 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1488 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1489 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1490 priv->prs_shadow[pe.index].finish = false;
1491 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
1493 mvpp2_prs_hw_write(priv, &pe);
1496 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1497 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1498 pe.index = MVPP2_PE_ETH_TYPE_UN;
1501 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1504 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1505 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1506 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
1509 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1514 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1515 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1516 priv->prs_shadow[pe.index].finish = true;
1517 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
1519 mvpp2_prs_hw_write(priv, &pe);
1533 struct mvpp2_prs_entry pe;
1567 memset(&pe, 0, sizeof(pe));
1568 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);
1569 pe.index = MVPP2_PE_VLAN_DBL;
1571 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID);
1574 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
1575 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE,
1578 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_DBL_VLAN_AI_BIT,
1581 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1584 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);
1585 mvpp2_prs_hw_write(priv, &pe);
1588 memset(&pe, 0, sizeof(pe));
1589 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);
1590 pe.index = MVPP2_PE_VLAN_NONE;
1592 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
1593 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,
1597 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1600 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);
1601 mvpp2_prs_hw_write(priv, &pe);
1609 struct mvpp2_prs_entry pe;
1619 memset(&pe, 0, sizeof(pe));
1620 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1621 pe.index = tid;
1623 mvpp2_prs_match_etype(&pe, 0, PPP_IP);
1624 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
1629 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
1630 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
1633 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN +
1637 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1641 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
1646 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
1647 mvpp2_prs_hw_write(priv, &pe);
1656 memset(&pe, 0, sizeof(pe));
1657 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1658 pe.index = tid;
1660 mvpp2_prs_match_etype(&pe, 0, PPP_IPV6);
1662 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
1663 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
1666 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
1670 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1675 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
1676 mvpp2_prs_hw_write(priv, &pe);
1684 memset(&pe, 0, sizeof(pe));
1685 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1686 pe.index = tid;
1688 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
1692 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1693 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1695 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1700 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
1701 mvpp2_prs_hw_write(priv, &pe);
1709 struct mvpp2_prs_entry pe;
1742 memset(&pe, 0, sizeof(pe));
1743 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
1744 pe.index = MVPP2_PE_IP4_PROTO_UN;
1747 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1748 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1751 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, -4,
1753 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);
1754 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,
1757 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
1760 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1763 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
1764 mvpp2_prs_hw_write(priv, &pe);
1767 memset(&pe, 0, sizeof(pe));
1768 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
1769 pe.index = MVPP2_PE_IP4_ADDR_UN;
1772 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
1774 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
1778 mvpp2_prs_sram_shift_set(&pe, -12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1780 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST,
1782 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);
1785 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1788 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
1789 mvpp2_prs_hw_write(priv, &pe);
1797 struct mvpp2_prs_entry pe;
1840 memset(&pe, 0, sizeof(pe));
1841 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
1842 pe.index = tid;
1845 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1846 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1847 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN |
1852 mvpp2_prs_tcam_data_byte_set(&pe, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK);
1853 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
1857 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
1858 mvpp2_prs_hw_write(priv, &pe);
1861 memset(&pe, 0, sizeof(pe));
1862 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
1863 pe.index = MVPP2_PE_IP6_PROTO_UN;
1866 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1867 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1868 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,
1871 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
1875 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
1878 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1881 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
1882 mvpp2_prs_hw_write(priv, &pe);
1885 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1886 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
1887 pe.index = MVPP2_PE_IP6_EXT_PROTO_UN;
1890 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1891 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1892 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,
1895 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_EXT_AI_BIT,
1898 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1901 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
1902 mvpp2_prs_hw_write(priv, &pe);
1905 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1906 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
1907 pe.index = MVPP2_PE_IP6_ADDR_UN;
1910 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
1911 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST,
1913 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
1916 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1918 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
1920 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1923 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);
1924 mvpp2_prs_hw_write(priv, &pe);
1933 struct mvpp2_prs_entry pe;
1944 mvpp2_prs_init_from_hw(port->priv, &pe, tid);
1946 mvpp2_prs_tcam_data_byte_get(&pe, 2, &byte[0], &enable[0]);
1947 mvpp2_prs_tcam_data_byte_get(&pe, 3, &byte[1], &enable[1]);
1968 struct mvpp2_prs_entry pe;
1971 memset(&pe, 0, sizeof(pe));
1994 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID);
1995 pe.index = tid;
1998 mvpp2_prs_tcam_port_map_set(&pe, 0);
2000 mvpp2_prs_init_from_hw(priv, &pe, tid);
2004 mvpp2_prs_tcam_port_set(&pe, port->id, true);
2007 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
2010 mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2013 mvpp2_prs_match_vid(&pe, MVPP2_PRS_VID_TCAM_BYTE, vid);
2016 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
2019 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID);
2020 mvpp2_prs_hw_write(priv, &pe);
2075 struct mvpp2_prs_entry pe;
2080 memset(&pe, 0, sizeof(pe));
2082 pe.index = tid;
2090 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID);
2093 mvpp2_prs_tcam_port_map_set(&pe, 0);
2096 mvpp2_prs_tcam_port_set(&pe, port->id, true);
2099 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
2102 mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2105 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
2109 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
2112 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID);
2113 mvpp2_prs_hw_write(priv, &pe);
2184 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
2191 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
2207 struct mvpp2_prs_entry pe;
2220 mvpp2_prs_init_from_hw(priv, &pe, tid);
2221 entry_pmap = mvpp2_prs_tcam_port_map_get(&pe);
2223 if (mvpp2_prs_mac_range_equals(&pe, da, mask) &&
2237 struct mvpp2_prs_entry pe;
2240 memset(&pe, 0, sizeof(pe));
2259 pe.index = tid;
2262 mvpp2_prs_tcam_port_map_set(&pe, 0);
2264 mvpp2_prs_init_from_hw(priv, &pe, tid);
2267 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
2270 mvpp2_prs_tcam_port_set(&pe, port->id, add);
2273 pmap = mvpp2_prs_tcam_port_map_get(&pe);
2278 mvpp2_prs_hw_inv(priv, pe.index);
2279 priv->prs_shadow[pe.index].valid = false;
2284 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
2289 mvpp2_prs_tcam_data_byte_set(&pe, len, da[len], 0xff);
2303 mvpp2_prs_sram_ri_update(&pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2305 mvpp2_prs_shadow_ri_set(priv, pe.index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2309 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
2313 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_MAC_DEF;
2314 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
2315 mvpp2_prs_hw_write(priv, &pe);
2344 struct mvpp2_prs_entry pe;
2357 mvpp2_prs_init_from_hw(priv, &pe, tid);
2359 pmap = mvpp2_prs_tcam_port_map_get(&pe);
2367 mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index],
2434 struct mvpp2_prs_entry pe;
2438 memset(&pe, 0, sizeof(pe));
2446 pe.index = tid;
2451 mvpp2_prs_sram_ai_update(&pe, flow, MVPP2_PRS_FLOW_ID_MASK);
2452 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2455 mvpp2_prs_tcam_data_byte_set(&pe, i, ri_byte[i],
2459 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
2460 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2461 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2462 mvpp2_prs_hw_write(priv, &pe);
2470 struct mvpp2_prs_entry pe;
2473 memset(&pe, 0, sizeof(pe));
2486 pe.index = tid;
2489 mvpp2_prs_sram_ai_update(&pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
2490 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2493 mvpp2_prs_shadow_set(port->priv, pe.index, MVPP2_PRS_LU_FLOWS);
2495 mvpp2_prs_init_from_hw(port->priv, &pe, tid);
2498 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2499 mvpp2_prs_tcam_port_map_set(&pe, (1 << port->id));
2500 mvpp2_prs_hw_write(port->priv, &pe);