Lines Matching refs:mvpp2_prs_sram_shift_set

303 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
509 		mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
573 			mvpp2_prs_sram_shift_set(&pe, shift,
627 		mvpp2_prs_sram_shift_set(&pe, 2 + MVPP2_ETH_TYPE_LEN + shift,
874 		mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN,
1006 	mvpp2_prs_sram_shift_set(&pe, -12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1086 	mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1161 	mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1175 	mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1262 	mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1288 	mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN,
1314 	mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_EDSA_LEN,
1348 	mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
1447 		mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN +
1477 	mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
1633 		mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN +
1666 	mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
1778 	mvpp2_prs_sram_shift_set(&pe, -12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1916 	mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2010 	mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2102 	mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2309 	mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,