marvell/mvpp2/mvpp2_main.c

183 					    struct mvpp2_tx_desc *tx_desc)
186 		return le32_to_cpu(tx_desc->pp21.buf_dma_addr);
188 		return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) &
193 				      struct mvpp2_tx_desc *tx_desc,
202 		tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr);
203 		tx_desc->pp21.packet_offset = offset;
207 		tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK);
208 		tx_desc->pp22.buf_dma_addr_ptp |= val;
209 		tx_desc->pp22.packet_offset = offset;
214 				    struct mvpp2_tx_desc *tx_desc)
217 		return le16_to_cpu(tx_desc->pp21.data_size);
219 		return le16_to_cpu(tx_desc->pp22.data_size);
223 				  struct mvpp2_tx_desc *tx_desc,
227 		tx_desc->pp21.data_size = cpu_to_le16(size);
229 		tx_desc->pp22.data_size = cpu_to_le16(size);
233 				 struct mvpp2_tx_desc *tx_desc,
237 		tx_desc->pp21.phys_txq = txq;
239 		tx_desc->pp22.phys_txq = txq;
243 				 struct mvpp2_tx_desc *tx_desc,
247 		tx_desc->pp21.command = cpu_to_le32(command);
249 		tx_desc->pp22.command = cpu_to_le32(command);
253 					    struct mvpp2_tx_desc *tx_desc)
256 		return tx_desc->pp21.packet_offset;
258 		return tx_desc->pp22.packet_offset;
309 			      struct mvpp2_tx_desc *tx_desc,
319 	tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc);
320 	tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) +
321 		mvpp2_txdesc_offset_get(port, tx_desc);
2476 	int tx_desc = txq->next_desc_to_proc;
2478 	txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
2479 	return txq->descs + tx_desc;
3691 	struct mvpp2_tx_desc *tx_desc;
3708 	tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
3709 	mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3710 	mvpp2_txdesc_size_set(port, tx_desc, xdpf->len);
3736 	mvpp2_txdesc_dma_addr_set(port, tx_desc, dma_addr);
3738 	mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
3739 	mvpp2_txq_inc_put(port, txq_pcpu, xdpf, tx_desc, buf_type);
4117 			       struct mvpp2_tx_desc *tx_desc,
4185 	tx_desc->pp22.ptp_descriptor &=
4187 	tx_desc->pp22.ptp_descriptor |=
4189 	tx_desc->pp22.buf_dma_addr_ptp &= cpu_to_le64(~0xffffff0000000000ULL);
4190 	tx_desc->pp22.buf_dma_addr_ptp |= cpu_to_le64((ptpdesc >> 12) << 40);
4202 	struct mvpp2_tx_desc *tx_desc;
4210 		tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4211 		mvpp2_txdesc_clear_ptp(port, tx_desc);
4212 		mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4213 		mvpp2_txdesc_size_set(port, tx_desc, skb_frag_size(frag));
4223 		mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
4227 			mvpp2_txdesc_cmd_set(port, tx_desc,
4229 			mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
4232 			mvpp2_txdesc_cmd_set(port, tx_desc, 0);
4233 			mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4243 		tx_desc = txq->descs + i;
4244 		tx_desc_unmap_put(port, txq, tx_desc);
4258 	struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4261 	mvpp2_txdesc_clear_ptp(port, tx_desc);
4262 	mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4263 	mvpp2_txdesc_size_set(port, tx_desc, hdr_sz);
4267 	mvpp2_txdesc_dma_addr_set(port, tx_desc, addr);
4269 	mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) |
4272 	mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4283 	struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4286 	mvpp2_txdesc_clear_ptp(port, tx_desc);
4287 	mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4288 	mvpp2_txdesc_size_set(port, tx_desc, sz);
4297 	mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
4300 		mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC);
4302 			mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
4306 		mvpp2_txdesc_cmd_set(port, tx_desc, 0);
4309 	mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4358 		struct mvpp2_tx_desc *tx_desc = txq->descs + i;
4359 		tx_desc_unmap_put(port, txq, tx_desc);
4370 	struct mvpp2_tx_desc *tx_desc;
4402 	tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4404 	    !mvpp2_tx_hw_tstamp(port, tx_desc, skb))
4405 		mvpp2_txdesc_clear_ptp(port, tx_desc);
4406 	mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4407 	mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb));
4417 	mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
4424 		mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
4425 		mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
4429 		mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
4430 		mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4434 			tx_desc_unmap_put(port, txq, tx_desc);