ethernet/marvell/mvneta.c

762 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
864 		mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
870 	mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
896 		mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
916 		mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
940 	mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
956 	mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
974 		mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1013 	mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
1024 	mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
1035 	mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
1048 	mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
1061 	mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
1080 	mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val);
1106 	mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
1107 	mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
1110 		mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
1112 	mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) |
1115 	mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000);
1119 	mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
1122 	mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
1247 	mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1);
1264 	mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
1274 	mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
1288 		mvreg_write(pp, MVNETA_RXQ_CMD,
1311 		mvreg_write(pp, MVNETA_TXQ_CMD,
1356 	mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1367 	mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1388 		mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
1405 		mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
1425 		mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
1435 	mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1448 	mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1449 	mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
1450 	mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
1460 	mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
1461 	mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
1462 	mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
1486 	mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
1489 	mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
1521 		mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
1525 	mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1526 	mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1529 	mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
1531 		mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
1532 		mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
1535 	mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1536 	mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1545 	mvreg_write(pp, MVNETA_ACC_MODE, val);
1548 		mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr);
1552 	mvreg_write(pp, MVNETA_PORT_CONFIG, val);
1555 	mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
1556 	mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
1571 	mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
1578 	mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
1585 	mvreg_write(pp, MVNETA_INTR_ENABLE,
1607 	mvreg_write(pp, MVNETA_TX_MTU, val);
1617 		mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1627 			mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1659 	mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1674 		mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1675 		mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1688 	mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1704 	mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1718 	mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1743 		mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1748 	mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
3094 	mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
3127 	mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
3187 		mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
3188 		mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
3195 	mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
3196 	mvreg_write(pp, MVNETA_TYPE_PRIO, val);
3241 	mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
3291 		mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
3329 			mvreg_write(pp, MVNETA_INTR_NEW_MASK,
3428 	mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
3429 	mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
3434 	mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
3435 	mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
3461 	mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
3462 	mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
3574 	mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
3575 	mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
3578 	mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
3579 	mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
3626 	mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
3627 	mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
3630 	mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
3631 	mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
3722 			mvreg_write(pp, MVNETA_SERDES_CFG,
3728 			mvreg_write(pp, MVNETA_SERDES_CFG,
3733 			mvreg_write(pp, MVNETA_SERDES_CFG,
3773 	mvreg_write(pp, MVNETA_INTR_MISC_MASK,
4056 		mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, an);
4067 	mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
4069 	mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
4106 		mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
4116 		mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER,
4166 		mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
4168 		mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2);
4170 		mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4);
4190 		mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, clk);
4203 		mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
4218 	mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1);
4234 		mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
4271 		mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
4283 		mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
4365 		mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
4430 	mvreg_write(pp, MVNETA_INTR_MISC_MASK,
4471 	mvreg_write(pp, MVNETA_INTR_MISC_MASK,
5010 	mvreg_write(pp, MVNETA_PORT_CONFIG, val);
5131 	mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0);
5143 	mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, 0);
5153 	mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val);
5175 	mvreg_write(pp, MVNETA_TXQ_CMD1_REG, val);
5178 	mvreg_write(pp, MVNETA_REFILL_NUM_CLK_REG, refill_cycles);
5188 	mvreg_write(pp, MVNETA_TXQ_CMD1_REG, val);
5214 	mvreg_write(pp, MVNETA_TXQ_BUCKET_REFILL_REG(queue), val);
5396 		mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
5397 		mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
5400 			mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
5410 			mvreg_write(pp, MVNETA_WIN_BASE(i),
5415 			mvreg_write(pp, MVNETA_WIN_SIZE(i),
5423 			mvreg_write(pp, MVNETA_WIN_BASE(0),
5430 		mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000);
5435 	mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
5436 	mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
5443 	mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);