ethernet/marvell/mv643xx_eth.c

193 	u32 cmd_sts;		/* Descriptor command status		*/
201 	u32 cmd_sts;		/* Command/status field			*/
207 	u32 cmd_sts;		/* Descriptor command status		*/
215 	u32 cmd_sts;		/* Command/status field			*/
515 		unsigned int cmd_sts;
521 		cmd_sts = rx_desc->cmd_sts;
522 		if (cmd_sts & BUFFER_OWNED_BY_DMA)
558 		if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
568 		if (cmd_sts & LAYER_4_CHECKSUM_OK)
579 		if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
586 		if (cmd_sts & ERROR_SUMMARY)
636 		rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
732 	u32 cmd_sts;
762 	cmd_sts = BUFFER_OWNED_BY_DMA;
765 		cmd_sts |= ZERO_PADDING | TX_LAST_DESC;
768 			cmd_sts |= TX_ENABLE_INTERRUPT;
770 	desc->cmd_sts = cmd_sts;
785 	u32 cmd_sts;
802 	cmd_sts = cmd_csum | BUFFER_OWNED_BY_DMA  | TX_FIRST_DESC |
809 		*first_cmd_sts = cmd_sts;
811 		desc->cmd_sts = cmd_sts;
872 	/* ensure all other descriptors are written before first cmd_sts */
874 	first_tx_desc->cmd_sts = first_cmd_sts;
914 			desc->cmd_sts = BUFFER_OWNED_BY_DMA |
918 			desc->cmd_sts = BUFFER_OWNED_BY_DMA;
936 	u32 cmd_sts;
940 	cmd_sts = 0;
949 	ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len);
952 	cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
964 		cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
977 	/* ensure all other descriptors are written before first cmd_sts */
979 	desc->cmd_sts = cmd_sts;
1069 		u32 cmd_sts;
1076 		cmd_sts = desc->cmd_sts;
1078 		if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1081 			desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1105 		if (cmd_sts & TX_ENABLE_INTERRUPT) {
1112 		if (cmd_sts & ERROR_SUMMARY) {
2087 		txd->cmd_sts = 0;