Lines Matching refs:lp
378 static dma_addr_t korina_tx_dma(struct korina_private *lp, int idx)
380 return lp->td_dma + (idx * sizeof(struct dma_desc));
383 static dma_addr_t korina_rx_dma(struct korina_private *lp, int idx)
385 return lp->rd_dma + (idx * sizeof(struct dma_desc));
406 struct korina_private *lp = netdev_priv(dev);
408 korina_abort_dma(dev, lp->tx_dma_regs);
413 struct korina_private *lp = netdev_priv(dev);
415 korina_abort_dma(dev, lp->rx_dma_regs);
422 struct korina_private *lp = netdev_priv(dev);
430 spin_lock_irqsave(&lp->lock, flags);
432 idx = lp->tx_chain_tail;
433 td = &lp->td_ring[idx];
436 if (lp->tx_count >= (KORINA_NUM_TDS - 2)) {
437 lp->tx_full = 1;
439 if (lp->tx_count == (KORINA_NUM_TDS - 2))
445 lp->tx_count++;
447 lp->tx_skb[idx] = skb;
452 ca = dma_map_single(lp->dmadev, skb->data, length, DMA_TO_DEVICE);
453 if (dma_mapping_error(lp->dmadev, ca))
456 lp->tx_skb_dma[idx] = ca;
462 if (readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
463 if (lp->tx_chain_status == desc_is_empty) {
468 lp->tx_chain_tail = chain_next;
470 writel(korina_tx_dma(lp, lp->tx_chain_head),
471 &lp->tx_dma_regs->dmandptr);
473 lp->tx_chain_head = lp->tx_chain_tail;
479 lp->td_ring[chain_prev].control &=
482 lp->td_ring[chain_prev].link = korina_tx_dma(lp, idx);
484 lp->tx_chain_tail = chain_next;
486 writel(korina_tx_dma(lp, lp->tx_chain_head),
487 &lp->tx_dma_regs->dmandptr);
489 lp->tx_chain_head = lp->tx_chain_tail;
490 lp->tx_chain_status = desc_is_empty;
493 if (lp->tx_chain_status == desc_is_empty) {
498 lp->tx_chain_tail = chain_next;
499 lp->tx_chain_status = desc_filled;
504 lp->td_ring[chain_prev].control &=
506 lp->td_ring[chain_prev].link = korina_tx_dma(lp, idx);
507 lp->tx_chain_tail = chain_next;
512 spin_unlock_irqrestore(&lp->lock, flags);
519 spin_unlock_irqrestore(&lp->lock, flags);
524 static int korina_mdio_wait(struct korina_private *lp)
528 return readl_poll_timeout_atomic(&lp->eth_regs->miimind,
535 struct korina_private *lp = netdev_priv(dev);
538 ret = korina_mdio_wait(lp);
542 writel(phy << 8 | reg, &lp->eth_regs->miimaddr);
543 writel(1, &lp->eth_regs->miimcmd);
545 ret = korina_mdio_wait(lp);
549 if (readl(&lp->eth_regs->miimind) & ETH_MII_IND_NV)
552 ret = readl(&lp->eth_regs->miimrdd);
553 writel(0, &lp->eth_regs->miimcmd);
559 struct korina_private *lp = netdev_priv(dev);
561 if (korina_mdio_wait(lp))
564 writel(0, &lp->eth_regs->miimcmd);
565 writel(phy << 8 | reg, &lp->eth_regs->miimaddr);
566 writel(val, &lp->eth_regs->miimwtd);
573 struct korina_private *lp = netdev_priv(dev);
577 dmas = readl(&lp->rx_dma_regs->dmas);
579 dmasm = readl(&lp->rx_dma_regs->dmasm);
582 &lp->rx_dma_regs->dmasm);
584 napi_schedule(&lp->napi);
598 struct korina_private *lp = netdev_priv(dev);
599 struct dma_desc *rd = &lp->rd_ring[lp->rx_next_done];
606 skb = lp->rx_skb[lp->rx_next_done];
643 ca = dma_map_single(lp->dmadev, skb_new->data, KORINA_RBSIZE,
645 if (dma_mapping_error(lp->dmadev, ca)) {
651 dma_unmap_single(lp->dmadev, lp->rx_skb_dma[lp->rx_next_done],
659 napi_gro_receive(&lp->napi, skb);
667 lp->rx_skb[lp->rx_next_done] = skb_new;
668 lp->rx_skb_dma[lp->rx_next_done] = ca;
674 rd->ca = lp->rx_skb_dma[lp->rx_next_done];
678 lp->rd_ring[(lp->rx_next_done - 1) &
682 lp->rx_next_done = (lp->rx_next_done + 1) & KORINA_RDS_MASK;
683 rd = &lp->rd_ring[lp->rx_next_done];
684 writel((u32)~DMA_STAT_DONE, &lp->rx_dma_regs->dmas);
687 dmas = readl(&lp->rx_dma_regs->dmas);
691 &lp->rx_dma_regs->dmas);
693 lp->dma_halt_cnt++;
695 rd->ca = lp->rx_skb_dma[lp->rx_next_done];
696 writel(korina_rx_dma(lp, rd - lp->rd_ring),
697 &lp->rx_dma_regs->dmandptr);
705 struct korina_private *lp =
707 struct net_device *dev = lp->dev;
714 writel(readl(&lp->rx_dma_regs->dmasm) &
716 &lp->rx_dma_regs->dmasm);
726 struct korina_private *lp = netdev_priv(dev);
754 &lp->eth_regs->ethhash0);
756 &lp->eth_regs->ethhash1);
759 spin_lock_irqsave(&lp->lock, flags);
760 writel(recognise, &lp->eth_regs->etharc);
761 spin_unlock_irqrestore(&lp->lock, flags);
766 struct korina_private *lp = netdev_priv(dev);
767 struct dma_desc *td = &lp->td_ring[lp->tx_next_done];
771 spin_lock(&lp->lock);
775 if (lp->tx_full == 1) {
777 lp->tx_full = 0;
780 devcs = lp->td_ring[lp->tx_next_done].devcs;
792 lp->tx_skb[lp->tx_next_done]->len;
819 if (lp->tx_skb[lp->tx_next_done]) {
820 dma_unmap_single(lp->dmadev,
821 lp->tx_skb_dma[lp->tx_next_done],
822 lp->tx_skb[lp->tx_next_done]->len,
824 dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
825 lp->tx_skb[lp->tx_next_done] = NULL;
828 lp->td_ring[lp->tx_next_done].control = DMA_DESC_IOF;
829 lp->td_ring[lp->tx_next_done].devcs = ETH_TX_FD | ETH_TX_LD;
830 lp->td_ring[lp->tx_next_done].link = 0;
831 lp->td_ring[lp->tx_next_done].ca = 0;
832 lp->tx_count--;
835 lp->tx_next_done = (lp->tx_next_done + 1) & KORINA_TDS_MASK;
836 td = &lp->td_ring[lp->tx_next_done];
841 dmas = readl(&lp->tx_dma_regs->dmas);
842 writel(~dmas, &lp->tx_dma_regs->dmas);
844 writel(readl(&lp->tx_dma_regs->dmasm) &
846 &lp->tx_dma_regs->dmasm);
848 spin_unlock(&lp->lock);
855 struct korina_private *lp = netdev_priv(dev);
859 dmas = readl(&lp->tx_dma_regs->dmas);
862 dmasm = readl(&lp->tx_dma_regs->dmasm);
864 &lp->tx_dma_regs->dmasm);
868 if (lp->tx_chain_status == desc_filled &&
869 (readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
870 writel(korina_tx_dma(lp, lp->tx_chain_head),
871 &lp->tx_dma_regs->dmandptr);
872 lp->tx_chain_status = desc_is_empty;
873 lp->tx_chain_head = lp->tx_chain_tail;
889 struct korina_private *lp = netdev_priv(dev);
891 mii_check_media(&lp->mii_if, 1, init_media);
893 if (lp->mii_if.full_duplex)
894 writel(readl(&lp->eth_regs->ethmac2) | ETH_MAC2_FD,
895 &lp->eth_regs->ethmac2);
897 writel(readl(&lp->eth_regs->ethmac2) & ~ETH_MAC2_FD,
898 &lp->eth_regs->ethmac2);
903 struct korina_private *lp = from_timer(lp, t, media_check_timer);
904 struct net_device *dev = lp->dev;
907 mod_timer(&lp->media_check_timer, jiffies + HZ);
922 struct korina_private *lp = netdev_priv(dev);
928 spin_lock_irq(&lp->lock);
929 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
930 spin_unlock_irq(&lp->lock);
931 korina_set_carrier(&lp->mii_if);
940 struct korina_private *lp = netdev_priv(dev);
944 strscpy(info->bus_info, lp->dev->name, sizeof(info->bus_info));
950 struct korina_private *lp = netdev_priv(dev);
952 spin_lock_irq(&lp->lock);
953 mii_ethtool_get_link_ksettings(&lp->mii_if, cmd);
954 spin_unlock_irq(&lp->lock);
962 struct korina_private *lp = netdev_priv(dev);
965 spin_lock_irq(&lp->lock);
966 rc = mii_ethtool_set_link_ksettings(&lp->mii_if, cmd);
967 spin_unlock_irq(&lp->lock);
968 korina_set_carrier(&lp->mii_if);
975 struct korina_private *lp = netdev_priv(dev);
977 return mii_link_ok(&lp->mii_if);
989 struct korina_private *lp = netdev_priv(dev);
996 lp->td_ring[i].control = DMA_DESC_IOF;
997 lp->td_ring[i].devcs = ETH_TX_FD | ETH_TX_LD;
998 lp->td_ring[i].ca = 0;
999 lp->td_ring[i].link = 0;
1001 lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail =
1002 lp->tx_full = lp->tx_count = 0;
1003 lp->tx_chain_status = desc_is_empty;
1010 lp->rx_skb[i] = skb;
1011 lp->rd_ring[i].control = DMA_DESC_IOD |
1013 lp->rd_ring[i].devcs = 0;
1014 ca = dma_map_single(lp->dmadev, skb->data, KORINA_RBSIZE,
1016 if (dma_mapping_error(lp->dmadev, ca))
1018 lp->rd_ring[i].ca = ca;
1019 lp->rx_skb_dma[i] = ca;
1020 lp->rd_ring[i].link = korina_rx_dma(lp, i + 1);
1025 lp->rd_ring[i - 1].link = lp->rd_dma;
1026 lp->rd_ring[i - 1].control |= DMA_DESC_COD;
1028 lp->rx_next_done = 0;
1029 lp->rx_chain_head = 0;
1030 lp->rx_chain_tail = 0;
1031 lp->rx_chain_status = desc_is_empty;
1038 struct korina_private *lp = netdev_priv(dev);
1042 lp->rd_ring[i].control = 0;
1043 if (lp->rx_skb[i]) {
1044 dma_unmap_single(lp->dmadev, lp->rx_skb_dma[i],
1046 dev_kfree_skb_any(lp->rx_skb[i]);
1047 lp->rx_skb[i] = NULL;
1052 lp->td_ring[i].control = 0;
1053 if (lp->tx_skb[i]) {
1054 dma_unmap_single(lp->dmadev, lp->tx_skb_dma[i],
1055 lp->tx_skb[i]->len, DMA_TO_DEVICE);
1056 dev_kfree_skb_any(lp->tx_skb[i]);
1057 lp->tx_skb[i] = NULL;
1067 struct korina_private *lp = netdev_priv(dev);
1074 writel(0, &lp->eth_regs->ethintfc);
1075 while ((readl(&lp->eth_regs->ethintfc) & ETH_INT_FC_RIP))
1079 writel(ETH_INT_FC_EN, &lp->eth_regs->ethintfc);
1088 writel(0, &lp->rx_dma_regs->dmas);
1090 writel(0, &lp->rx_dma_regs->dmandptr);
1091 writel(korina_rx_dma(lp, 0), &lp->rx_dma_regs->dmadptr);
1093 writel(readl(&lp->tx_dma_regs->dmasm) &
1095 &lp->tx_dma_regs->dmasm);
1096 writel(readl(&lp->rx_dma_regs->dmasm) &
1098 &lp->rx_dma_regs->dmasm);
1101 writel(ETH_ARC_AB, &lp->eth_regs->etharc);
1104 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
1105 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
1107 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
1108 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
1110 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
1111 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
1113 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
1114 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
1119 &lp->eth_regs->ethmac2);
1122 writel(0x15, &lp->eth_regs->ethipgt);
1124 writel(0x12, &lp->eth_regs->ethipgr);
1128 writel(((lp->mii_clock_freq) / MII_CLOCK + 1) & ~1,
1129 &lp->eth_regs->ethmcp);
1130 writel(0, &lp->eth_regs->miimcfg);
1133 writel(48, &lp->eth_regs->ethfifott);
1135 writel(ETH_MAC1_RE, &lp->eth_regs->ethmac1);
1139 napi_enable(&lp->napi);
1150 struct korina_private *lp = container_of(work,
1152 struct net_device *dev = lp->dev;
1157 disable_irq(lp->rx_irq);
1158 disable_irq(lp->tx_irq);
1160 writel(readl(&lp->tx_dma_regs->dmasm) |
1162 &lp->tx_dma_regs->dmasm);
1163 writel(readl(&lp->rx_dma_regs->dmasm) |
1165 &lp->rx_dma_regs->dmasm);
1167 napi_disable(&lp->napi);
1177 enable_irq(lp->tx_irq);
1178 enable_irq(lp->rx_irq);
1183 struct korina_private *lp = netdev_priv(dev);
1185 schedule_work(&lp->restart_task);
1199 struct korina_private *lp = netdev_priv(dev);
1211 ret = request_irq(lp->rx_irq, korina_rx_dma_interrupt,
1215 dev->name, lp->rx_irq);
1218 ret = request_irq(lp->tx_irq, korina_tx_dma_interrupt,
1222 dev->name, lp->tx_irq);
1226 mod_timer(&lp->media_check_timer, jiffies + 1);
1231 free_irq(lp->rx_irq, dev);
1239 struct korina_private *lp = netdev_priv(dev);
1242 del_timer(&lp->media_check_timer);
1245 disable_irq(lp->rx_irq);
1246 disable_irq(lp->tx_irq);
1249 tmp = readl(&lp->tx_dma_regs->dmasm);
1251 writel(tmp, &lp->tx_dma_regs->dmasm);
1254 tmp = readl(&lp->rx_dma_regs->dmasm);
1256 writel(tmp, &lp->rx_dma_regs->dmasm);
1258 napi_disable(&lp->napi);
1260 cancel_work_sync(&lp->restart_task);
1264 free_irq(lp->rx_irq, dev);
1265 free_irq(lp->tx_irq, dev);
1287 struct korina_private *lp;
1298 lp = netdev_priv(dev);
1309 lp->mii_clock_freq = clk_get_rate(clk);
1311 lp->mii_clock_freq = 200000000; /* max possible input clk */
1314 lp->rx_irq = platform_get_irq_byname(pdev, "rx");
1315 lp->tx_irq = platform_get_irq_byname(pdev, "tx");
1322 lp->eth_regs = p;
1329 lp->rx_dma_regs = p;
1336 lp->tx_dma_regs = p;
1338 lp->td_ring = dmam_alloc_coherent(&pdev->dev, TD_RING_SIZE,
1339 &lp->td_dma, GFP_KERNEL);
1340 if (!lp->td_ring)
1343 lp->rd_ring = dmam_alloc_coherent(&pdev->dev, RD_RING_SIZE,
1344 &lp->rd_dma, GFP_KERNEL);
1345 if (!lp->rd_ring)
1348 spin_lock_init(&lp->lock);
1350 dev->irq = lp->rx_irq;
1351 lp->dev = dev;
1352 lp->dmadev = &pdev->dev;
1357 netif_napi_add(dev, &lp->napi, korina_poll);
1359 lp->mii_if.dev = dev;
1360 lp->mii_if.mdio_read = korina_mdio_read;
1361 lp->mii_if.mdio_write = korina_mdio_write;
1362 lp->mii_if.phy_id = 1;
1363 lp->mii_if.phy_id_mask = 0x1f;
1364 lp->mii_if.reg_num_mask = 0x1f;
1374 timer_setup(&lp->media_check_timer, korina_poll_media, 0);
1376 INIT_WORK(&lp->restart_task, korina_restart_task);